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1 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.1 description the 7640 group, an enhanced family of cmos 8-bit microcontrollers, offers high-speed operation, large internal-memory options, and a wide variety of stan- dard peripherals. the series is code compatible with the 38000, 7200, 7400, and the 7500 series, and pro- vides many performance enhancements to the instruction set. this device is a single chip pc peripheral microcon- troller based on the universal serial bus (usb) version 1.1 specification. this device provides data exchange between a usb-equipped host computer and pc peripherals such as telephones, audio sys- tems and digital cameras. see figure 1.1 for a pin layout diagram. see figure 1.2 for the functional block diagram. 1.2 mcu features ? number of basic instructions ................................ 71 ? minimum instruction execution time ................. 83ns (1-cycle instruction = 12 mhz) ?clock frequency maximum .................. f(x in ) = 24 mhz ........................................................ f(xc in ) = 5 mhz ............................................................ = 12 mhz ? memory size rom .................................................. 32kb on chip ram ................................................... 1 kb on chip ? programmable i/o ports ...................................... 66 .................................................... 8 bit x 7, 5 bit x 2 ? master bus interface (mbi) ... .................... 17 signals ............................................................. 8 data lines ? serial i/o ............................. 8 bit clock synchronous ? usb function control .............. 4 endpoints,1 control ? interrupts ................................ 4 external, 19 internal ................................................ 1 software,1 system ? dmac .......................... 2 channels, 16 address lines (max. 6m byte/sec. transfer speed in burst mode) ? timers ......................................... 8 bit x 3, 16 bit x 2 ? number of full duplex uarts available ................... 2 ? supply voltage ............................. v cc = 4.15~5.25v ? operating temperature range ................... -20 to 85c ? power-saving modes ..... wit (idle), stp (clocks halt) 1.3 applications cameras, games, musical instruments, modems scanners, and pc peripherals. fig. 1.1. pin layout package outline: 80p6n-a p3 0 /rd y p7 4 /obf 1 p4 0 / edma 41 40 24 65 p7 3 / ibf 1 / hld a 66 p7 2 / s1 67 p7 1 /( hold) 68 p7 0 /( sof) 69 usb d+ 70 usb d- 71 ext. cap 72 v ss 73 v cc 74 p6 7 /dq7 75 p6 6 /dq6 76 p6 5 /dq5 77 p6 4 /dq4 78 p6 3 /dq3 79 p6 2 /dq2 80 p4 1 /int0 23 p4 2 /int1 22 p4 3 /cntr0 21 p4 4 /cntr1 20 lpf 19 a v ss 18 a v cc 17 v cc 16 x out 15 x in 14 v ss 13 p5 0 /xc in 12 p5 1 /t out /xc out 11 reset 10 cnvss/vpp 9 p5 2 /obf 0 8 p5 3 / ibf 0 7 p5 4 / s 0 6 p5 5 /a 0 5 p5 6 / r(e) 4 p5 7 / w(r/ w) 3 p6 0 /dq0 2 p6 1 /dq1 1 p3 1 39 p3 2 38 p3 3 /dma out 37 p3 4 / out 36 p3 5 /sync out 35 p3 6 / wr 34 p3 7 / rd 33 p8 0 /utxd2/ srd y 32 p8 1 /urxd2/sclk 31 p8 2 / cts2/srxd 30 p8 3 / r ts2/stxd 29 p8 4 /utxd1 28 p8 5 /urxd1 27 p8 6 / cts1 26 p8 7 / r ts1 25 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p1 7 /ab15 p1 6 /ab14 p1 5 /ab13 p1 4 /ab12 p1 3 /ab11 p1 2 /ab10 p1 1 /ab9 p1 0 /ab8 p0 7 /ab7 p0 6 /ab6 p0 5 /ab5 p0 4 /ab4 p0 3 /ab3 p0 2 /ab2 p0 1 /ab1 p0 0 /ab0 p2 7 /db7 p2 6 /db6 p2 5 /db5 p2 4 /db4 p2 3 /db3 p2 2 /db2 p2 1 /db1 p2 0 /db0 m37640e8fp m37640m8-xxxfp _
2 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.4 functional block diagram fig. 1.2. functional block diagram t out c p u a x y s pc h pc l ps reset v cc v ss r o m r a m 10 16 13 p2(8) p0(8) p1(8) p3(8) p5(8) 49 50 51 52 53 54 55 56 41 42 43 44 45 46 47 48 57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 p6(8) 20 21 22 23 24 x in out x cout x x cin 14 15 75 76 77 78 79 80 12 p7(5) 65 66 67 69 68 p8(8) 25 26 27 28 29 30 31 32 d+ d- x cin cntr 1 ,cntr 0 usb v cc 74 v ss 73 cnv ss 9 uart1(8) uart2(8) sof 70 71 3456781112 w(r/w) r(e),a 0 s 0 ,ibf 0 obf 0 int 1 , int 0 p4(5) dma ext.cap 72 lpf 18 av ss 19 s 1 ,ibf 1 obf 1 t out 36 35 40 24 33 34 66 68 17 avcc frequency synthesizer 12 11 edma rd wr syncout rdy hlda hold timer x (16) timer y (16) timer 1 (8) timer 2 (8) timer 3 (8) p8 p7 sio (8) mbi dq (0-7) p6 p5 p4 p3 dma out p2 p1 key-on wake-up p0
3 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.5 pin description and layout table 1.1. pin description and layout name i/o description pin # p0 0 /ab0~ p1 7 /ab15 i/o cmos i/o port (address bus). when the mcu is in memory expansion or microprocessor mode, these pins function as the address bus. 56-41 p2 0 /db0 ~ p2 7 /db7 i/o cmos i/o port (data bus). when the mcu is in memory expansion or microprocessor mode, these pins function as the data bus. these pins may also be used to implement the key-on wake up function. 64-57 p3 0 /rdy i/o cmos i/o port (ready). when the mcu is in memory expansion or microprocessor mode, this pin functions as rdy (hardware wait cycle control). 40 p3 1 i/o cmos i/o port. 39 p3 2 i/o cmos i/o port. 38 p3 3 /dma out i/o cmos i/o port (dma out ). when the mcu is in memory expansion or microprocessor mode, this pin is set to a ?1? during a dma transfer. 37 p3 4 / out i/o cmos i/o port . when the mcu is in memory expansion or microprocessor mode, this pin becomes out pin. 36 p3 5 /sync out i/o cmos i/o port (sync out ). when the mcu is in memory expansion or microprocessor mode, this pin becomes the sync out pin. 35 p3 6 /wr i/o cmos i/o port. (wr output). when the mcu is in memory expansion or microprocessor mode, this pin becomes wr. 34 p3 7 /rd i/o cmos i/o port. (rd output). when the mcu is in memory expansion or microprocessor mode, this pin becomes rd. 33 p4 0 /edma i/o cmos i/o port (edma: expanded data memory access). when the mcu is in memory expansion or microprocessor mode, this pin can become the edma pin. 24 p4 1 /int0~ p4 2 /int1 i/o cmos i/o port or external interrupt ports int0 and int1. these external interrupts can be configured to be active high or low. 23-22 p4 3 /cntr0 i/o cmos i/o port or timer x input pin for pulse width measurement mode and event counter mode or timer x output pin for pulse output mode. this pin can also be used as an external interrupt when timer x is not in output mode. the interrupt polarity is selected in the timer x mode register. 21 p4 4 /cntr1 i/o cmos i/o port or timer y input pin for pulse period measurement mode, pulse h-l measurement mode and event counter mode or timer y output pin for pulse output mode. this pin can also be used as an external interrupt when timer y is not in output mode. the interrupt polarity is selected in the timer y mode register. 20 p5 0 /xc in i/o cmos i/o port or xc in .12 p5 1 /tout/xc out i/o cmos i/o port or timer half pulse output pin (can be configured initially high or initially low), or xcout. 11 p5 2 /obf 0 i/o cmos i/o port or obf 0 output to master cpu for data bus buffer 0. 8 p5 3 /ibf 0 i/o cmos i/o port or ibf 0 output to master cpu for data bus buffer 0. 7 p5 4 /s 0 i/o cmos i/o port or s 0 input from master cpu for data bus buffer 0. 6 p5 5 /a 0 i/o cmos i/o port or a 0 input from master cpu. 5 p5 6 /r(e) i/o cmos i/o port or r(e) input from master cpu. 4 p5 7 /w(r/w) i/o cmos i/o port or w(r/w) input from master cpu. 3 p6 0 /dq0~ p6 7 /dq7 i/o cmos i/o port or master cpu data bus. 2-1, 80-75 usb d- i/o usb d- voltage line interface, a series resistor of 33 ? should be connected to this pin. 71 usb d+ i/o usb d+ voltage line interface, a series resistor of 33 ? should be connected to this pin. 70 p7 0 /sof i/o cmos i/o port or usb start of frame pulse output, an 80 ns pulse outputs on this pin for every usb frame. 69 p7 1 /hold i/o cmos i/o port or hold pin. 68 p7 2 /s 1 i/o cmos i/o port or s 1 input from master cpu for data bus buffer 1. 67
4 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer name i/o description pin # p7 3 /ibf 1 /hlda i/o cmos i/o port or ibf 1 output to master cpu for data bus buffer 1, or hlda pin. ibf 1 and hlda are mutually exclusive. ibf 1 has priority over hlda 66 p7 4 /obf 1 i/o cmos i/o port or obf 1 output to master cpu for data bus buffer 1. 65 p8 0 /utxd2/srdy i/o cmos i/o port or uart2 pin utxd2 or sio pin srdy. uart2 and sio are mutually exclusive, uart2 has priority over sio. 32 p8 1 /urxd2/sclk i/o cmos i/o port or uart2 pin urxd2 or sio pin sclk. uart2 and sio are mutually exclusive, uart2 has priority over sio. 31 p8 2 /cts2/srxd i/o cmos i/o port or uart2 pin cts2 or sio pin srxd. uart2 and sio are mutually exclusive, uart2 has priority over sio. 30 p8 3 /rts2/stxd i/o cmos i/o port or uart2 pin rts2 or sio pin stxd. uart2 and sio are mutually exclusive, uart2 has priority over sio. 29 p8 4 /utxd1 i/o cmos i/o port or uart1 pin utxd1. 28 p8 5 /urxd1 i/o cmos i/o port or uart1 pin urxd1. 27 p8 6 /cts1 i/o cmos i/o port or uart1 pin cts1. 26 p8 7 /rts1 i/o cmos i/o port or uart1 pin rts1. 25 av cc , av ss i power supply inputs for analog circuitry avcc = 4.15~ 5.25v, avss = 0v 17,19 cnv ss /v pp i controls the processor mode of the chip. normally connected to v ss or v cc . when the mcu is in eprom program mode, this pin supplies the programming voltage to the eprom. 9 v cc ,v ss i power supply inputs: v cc = 4.15~ 5.25v, v ss = 0v 16/74 13/73 reset i to enter the reset state, this pin must be kept 'l' for more that 2 s (20 cycles under normal v cc conditions). if the crystal or ceramic resonator requires more time to stabilize, extend this 'l' level time appropriately. 10 xc in i 12 xc out o an external ceramic or quartz crystal oscillator can be connected between the xc in and xc out pins. if an external clock source is used, connect the clock source to the xc in pin and leave the xc out pin open. 11 x in i 14 x out o input and output signals to and from the internal clock generation circuit. connect a ceramic resonator or quartz crystal between x in and x out pins to set the oscillation frequency. if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. 15 lpf o loop filter for the frequency synthesizer. 18 ext. cap i an external capacitor (ext. cap) pin. when the usb transceiver voltage converter is used, a 2 f or larger capacitor should connect between this pin and vss to ensure proper operation of the usb line driver. the voltage converter is enabled by setting bit 4 of the usb control register (0013 16 ) to a ? 1 ? . 72
5 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.6 part numbering t ype no . rom capacity ram capacity package type remarks m37640m8-xxxfp 32k bytes 1 k bytes 80p6n-a mask rom version m 37640e8fp 32k bytes 1 k bytes 80p6n-a one-time prom version m37640e8fs 32k bytes 1 k bytes 80d0 eprom version fig. 1.3. type no., memory size, and package 1.7 rom expansion table 1.2. rom expansion 1.8 currently supported products table 1.3. currently supported products m37 m 8 -xxx fp package type: fp: 80p6n fs: 80d0 rom number rom capacity: 32 kbytes memory type: m: mask rom version e: eprom version one-time prom version g roup 7600 series 640 7640 rom size (bytes) 32k m37640m8-xxxfp m37640e8fp m37640e8fs mask rom version one-time prom version eprom version
6 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.9 central processing unit the central processing unit (cpu) has six registers: ? accumulator (a) ? index register x (x) ? index register y (y) ? stack pointer (s) ? processor status register (ps) ? program counter (pc) 1.9.1 register structure five of the cpu registers are 8-bit registers. these are the accumulator (a), index register x (x), index regis- ter y (y), stack pointer (s), and the processor status register (ps) as shown in figure 1.4. the program counter (pc) is a 16-bit register consist- ing of two 8-bit registers (pch and pcl). after a hardware reset, bit 2 (i flag) of the ps is set high and the values at the address fffa 16 and fffb 16 are stored in the pc, but the values of the other bits of the ps and other registers are undefined. initialization of the undefined registers may be neces- sary for some programs. 0 7 accumulator 0 7 index register x 0 7 index register y 0 7 stack pointer 0 7 pc l 15 pc h 0 7 carry flag (bit 0) zero flag (bit 1 ) interrupt disable flag (bit 2) decimal mode flag (bit 3) break flag (bit 4) index x mode flag (bit 5) overflow flag (bit 6) negative flag (bit 7) program counter d i z c n v t b processor status register fig. 1.4. register structure
ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 7 1.10 cpu mode registers this device has two cpu mode registers: ? cpu mode register a (cpma) ? cpu mode register b (cpmb) these registers control the processor mode, clock, slow memory wait and other cpu functions. the bit representation of each register is described in figure 1.5 and figure 1.6. fig. 1.5. cpu mode register a (cpma) fig.1.6. cpu mode register b (cpmb) cpma7 cpma5 cpma4 reserved cpma2 cpma1 cpma0 msb 7 lsb 0 address: 0000 16 access: r/w reset: oc 16 cpma6 cpma0,1 processor mode bits (bits 1,0) bit 1 bit 0 0 0: single-chip mode 0 1: memory expansion mode 1 0: microprocessor mode 1 1: not used cpma2 stack page selection bit (bit 2) 0: in page 0 area 1: in page 1 area cpma3 reserved (read/write ?1?) cpma4 clock xc in - xc out stop bit (bit 4) 0: stop 1: oscillator cpma5 clock x in - x out stop bit (bit 5) 0: oscillator 1: stop cpma6 internal clock selection bit (bit 6) 0: external clock 1: f syn cpma7 external clock selection bit (bit 7) 0: x in - x out 1: xc in - xc out cpmb0,1 slow memory wait bits (bits 1,0) bit 1 bit 0 0 0: no wait 0 1: one time wait 1 0: two time wait 1 1: three time wait cpmb2,3 slow memory mode bit (bit 3,2) bit 3 bit 2 0 0: software wait 0 1: not used 1 0: fixed wait by rdy pin l 1 1: extended rdy wait cpb4 expanded data memory access bit (bit 4) 0:edma output disabled (64 kbyte data access area) 1:edma output enabled (greater than 64 kbytes data access area) cpmb5 hold function enable bit (bit 5) 0:hold function disabled 1:hold function enabled cpmb6 r eserved (read/write ?0?) cpmb7 r eserved (read/write ?1?) cpmb5 cpmb4 cpmb2 cpmb1 cpmb0 msb 7 lsb 0 address: 0001 16 access: r/w reset: 83 16 cpmb3 reserved reserved
8 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.11 memory map the first 112 bytes of memory from 0000 16 to 006f 16 is the special function register (sfr) area and con- tains the cpu mode registers, interrupt registers, and other registers to control peripheral functions (see figure 1.7). the general purpose ram resides from 0070 16 to 046f 16. when the mcu is in memory expansion or microprocessor mode and external memory is over- laid on the internal ram, the cpu reads data from the internal ram. however, the cpu writes data in both the internal and external memory. the area from 0470 16 to 7fff 16 is not used in single-chip mode, but can be mapped for an external memory device when the mcu is in memory expansion or microprocessor mode. the area from 8000 16 to 807f 16 and from fffc 16 to ffff 16 are factory reserved areas. mitsubishi uses it for test and evaluation purposes. the user can not use this area in single-chip or memory expansion modes. the user 32k byte rom resides from 8080 16 to fffb 16. when the mcu is in microprocessor mode, the cpu accesses an external area rather than ac- cessing the internal rom. 1.11.1 special page the 256 bytes from address ff00 16 to ffff 16 are called the special page area. in this area special page addressing can be used to specify memory ad- dresses. this dedicated special page addressing mode enables access to this area with fewer instruc- tion cycles. frequently used subroutines are normally stored in this area. fig. 1.7. memory map sfr area reserved area zero page special page for subroutine calls not used reserved area 0000 16 006f 16 0070 16 00ff 16 0100 16 046f 16 0470 16 7fff 16 8000 16 807f 16 8080 16 feff 16 ff00 16 ffc9 16 ffca 16 fffb 16 fffc 16 ffff 16 ram 1k bytes rom interrupt ve c t o r bytes 32k
ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 9 1.12 processor modes the operation modes are described below. the memory maps for the first three modes are shown in figure 1.8. single chip mode is normally entered after reset. how- ever, if the mcu has a cnvss pin, holding this pin high will cause microprocessor mode to be entered after re- set. after the reset sequence has completed, the mode can be changed with software by modifying the value of bits 0 and 1 of cpma. however, while cnvss is high, bit 1 of cpma is ?1? and cannot be changed. single chip mode memory expansion mode microprocessor mode cpma, cpmb and int registers p0 - p3 internal ram (zero page) internal ram inaccessible area reserved area rom interrupt vectors reserved area 0000 0007 0008 000f 0010 006f 0070 00ff 0100 046f 0470 7fff 8000 807f 8080 ffc9 ffca fffb fffc ffff cpma, cpmb and int registers external memory internal ram (zero page) internal ram external memory reserved area rom interrupt vectors reserved area 0000 0007 0008 000f 0010 006f 0070 00ff 0100 046f 0470 7fff 8000 807f 8080 ffc9 ffca fffb fffc ffff cpma, cpmb and int registers external memory internal ram (zero page) internal ram external memory 0000 0007 0008 000f 0010 006f 0070 00ff 0100 046f 0470 ffff sfr sfr sfr fig. 1.8. operation modes memory maps
10 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.12.1 single chip in this mode, all ports take on their primary function and all internal memory is accessible. those areas that are not in internal memory are not accessible. also, slow memory wait and edma are disabled in this mode. 1.12.2 memory expansion in this mode, ports 0 and 1 output the address bus (ab0-ab15), port 2 acts as the data bus input and out- put, and port 3 bits 7 to 3 output rd, wr, sync out , out , and dma out , respectively. all memory areas that are not internal memory or sfr area are accessed externally. because ports 0 to 3 lose their normal function in this mode, the address area for the ports and their direction registers are treated as external memory. in this mode, slow memory wait and edma can be enabled. 1.12.3 microprocessor this mode is primarily the same as memory expansion mode. the difference is that the internal rom/eprom area can not be accessed and is instead treated as external memory. slow memory wait and edma can be enabled in this mode. 1.12.4 slow memory wait the wait function is used when interfacing with external memories that are too slow to operate at the normal read/write speed of the mcu. when this is the case, a wait can be used to extend the read/write cycle. three different wait modes are supported; software wait, rdy wait, and extended rdy wait. the appropriate mode is chosen by the setting of bits 0 to 3 of cpmb. the wait function is disabled for internal memory and is valid only for memory expansion and microprocessor modes. software wait is used to extend the read/write cycle by one, two, or three cycles of . the cycle number is determined by the value of bits 0 and 1 of cpmb. when software wait is selected, the value on the rdy pin is ignored. the timing for software wait is shown in figure 1.9. rdy wait is also used to extend the read/write cycle by one, two, or three cycles . in this case, the read/write cycle is extended if the rdy pin is low when out goes low (taking into account setup and hold times) at the beginning of the read/write cycle. the extension time is fixed by the value of bits 0 and 1 of cpmb and does not depend on the state of the rdy pin once the read/write cycle has begun. if the rdy pin is high when out goes low at the beginning of the read/write cycle, the read/ write cycle is not extended. the timing for rdy wait is shown in figure 1.10. the extended rdy wait mode is used to extend the read/write cycle by a variable number of cycles of the exact number is dependent on the state of the rdy pin and the value of bits 0 and 1 of cpmb. in this mode, the read/write cycle is extended if the rdy pin is low when out goes low at the beginning of the read/write cycle. the read/write cycle continues to be extended until the rdy pin is high when out goes low, at which point the read/write cycle completes in one, two, or three cycles of (with respect to the previous low to high transition of ), dependent on the value in bits 0 and 1 of cpmb. if the rdy pin is high when out goes low at the beginning of the read/write cycle, the read/write cycle is not extended. the timing for this mode is shown in figure 1.11. the wait function can only be enabled for external memory access in microprocessor or memory expan- sion modes. however, the wait function can not be en- abled for accesses to addresses 0008 16 to 000f 16 (port 0 through port 3 registers) in these modes, even though the locations are mapped as external memory.
ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 11 in out in out in out no wait cpmb = 00 16 one time s/w wait cpmb = 01 16 two time s/w wait cpmb = 02 16 in out three time s/w wait internal signals x in p1 p2 out ad out db in/out rd wr rdy x in p1 p2 out ad out db in/out rd wr rd fig. 1.9. software wait timing diagram
12 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer fig. 1.10. rdy wait timing diagram in out in out in out no wait cpmb = 08 16 one time fixed wait cpmb = 09 16 two time fixed wait cpmb = 0a 16 in out three time fixed wait cpmb = 0b 16 internal signals t su t su t su t su t su t su x in p1 p2 out ad out db in/out rd wr rdy x in p1 p2 out ad out db in/out rd wr rdy
ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 13 fig. 1.11. extended rdy wait timing diagram in out in out no wait cpmb = 0c 16 one time extended rdy wait cpmb = 0d 16 two time extended rdy wait cpmb = 0e 16 in out two time extended rdy wait cpmb = oe 16 internal signals t su t su t su t su t su t su three time extended rdy wait cpmb = 0f 16 in t su t su t su t su t su t su t su t su t su out t su t su t su t su t su t su t su t su t su t su t su t su t su t su t su x in p1 p2 out ad out db in/out rd wr rdy x in p1 p2 out ad out db in/out rd wr rdy ///////// /////////
14 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.12.5 hold function the hold function is used when the mcu is put in a system where more than one device will need control of the external address and data buses. two signals are used to implement this function, hold (p7 1 ) and hlda (p7 3 ). hold is an input to the mcu and is brought low when an external device wants the mcu to relinquish the address and data buses. hlda is an output from the mcu that signals when the mcu has relinquished the buses. when this is the case, the mcu tri-state ports 0 and 1 (address bus) and port 2 (data bus), and holds port p3 7 (rd) and port p3 6 (wr) high. ports p3 7 and p3 6 are held high to pre- vent any external device that is enabled by rd or wr from being falsely activated. the clocks to the cpu are stopped, but the peripheral clocks and port p3 4 ( out ) continue to oscillate. hold is brought high to allow the mcu to regain the address and data buses. when this occurs, hlda will go high and ports p 1 , p 2 , p3 7 and p3 6 will begin to drive the external buses again. the timing for the hold function is shown in fig- ure 1.12. the hold function is only valid for memory expansion and microprocessor modes. bit 5 of cpmb is used to enable the hold function. hlda will loose its function when the ibf 1 pin functionality is used. 1.12.6 expanded data memory access the expanded data memory access (edma) mode feature allows the user to access a greater than 64 kbyte data area for instructions lda (indy) with t=?0? and t=?1?, and sta (indy). bit 4 of cpmb is used to enable/disable the edma function. if bit 4 of cpmb equals ?1?, then during the data read/write cycle of in- structions lda (indy) and sta (indy) port 4 0 (edma) is driven low. the edma signal output can be used by an external decoder to indicate when the read/write is to a different 64 kbyte bank. the actual determination of which bank to access can be done by using a few bits of a port to represent the extended addresses above ab15. for example, if four banks are accessed, then two bits are needed to uniquely identify each bank. two port bits can be used for this, one repre- senting ab16 and the other ab17. the instruction sequences for sta (indy) and lda (indy) are shown in figure 1.13 and figure 1.14. fig. 1.12. hold function timing diagram x in out rd , wr addr out data in/out hold hlda t su (hold - out ) t h ( out -hold ) t d ( out -hlda ) t d ( out -hlda ) ------ ------ ------ ------ ------ //////// ////////
ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 15 fig. 1.13. instruction sequences for sta ($zz) indy with edma enable fig. 1.14. instruction sequences for lda ($zz) indy with edma enable sync out rd wr address data adh invalid data next adl+y, adl+y,adh bal+1, 00 bal, 00 pc +1 pc pc + 2 opcode adh+c b1 bal adl edma [lda ($zz),y (t = ?0?)] instruction sequence (edma ) [lda ($zz),y (t = ?1?)] instruction sequence (edma ) adh invalid data next adl+y, adl+y,adh bal+1, 00 bal, 00 pc +1 pc pc 2 opcode adh+c b1 bal adl x, 00 invalid data sync out rd wr address data edma sync out rd wr address data adh invalid data next adl+y, adl+y,adh bal+1, 00 bal, 00 pc +1 pc pc + 2 opcode adh+c 91 bal adl edma
16 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.13 special function registers the special function registers (sfr) are used for controlling the functional blocks, such as i/o ports, timers, uart, and so forth (see table 1.4). the re- served addresses should not be read or written to. table 1.4. sfr addresses addr description acronym and value at reset addr description acronym and value at reset 0000 16 cpu mode register a cpma=0c 0038 16 uart2 mode register u2mod=00 0001 16 cpu mode register b cpmb=83 0039 16 uart2 baud rate generator u2brg=xx 0002 16 interrupt request register a ireqa=00 003a 16 uart2 status register u2sts=03 0003 16 interrupt request register b ireqb=00 003b 16 uart2 control register u2con=00 0004 16 interrupt request register c ireqc=00 003c 16 uart2 transmit/receiver buffer 1 u2trb1=xx 0005 16 interrupt control register a icona=00 003d 16 uart2 transmit/receiver buffer 2 u2trb2=xx 0006 16 interrupt control register b iconb=00 003e 16 uart2 rts control register u2rtsc=80 0007 16 interrupt control register c iconc=00 003f 16 dmac index and status register dmais=00 0008 16 port p0 p0=00 0040 16 dmac channel x mode register 1 dmaxm1=00 0009 16 port p0 direction register p0d=00 0041 16 dmac channel x mode register 2 dmaxm2=00 000a 16 port p1 p1=00 0042 16 dmac channel x source register low dmaxsl=00 000b 16 port p1 direction register p1d=00 0043 16 dmac channel x source register high dmaxsh=00 000c 16 port p2 p2=00 0044 16 dmac channel x destination register low dmaxdl=00 000d 16 port p2 direction register p2d=00 0045 16 dmac channel x destination register high dmaxdh=00 000e 16 port p3 p3=00 0046 16 dmac channel x count register low dmaxcl=00 000f 16 port p3 direction register p3d=00 0047 16 dmac channel x count register high dmaxch=00 0010 16 port control register ptc=00 0048 16 data bus buffer register 0 dbb0=00 0011 16 interrupt polarity selection register ipol=00 0049 16 data bus buffer status register 0 dbbs0=00 0012 16 port p2 pull-up control register pup2=00 004a 16 data bus buffer control register 0 dbbc0=00 0013 16 usb control register usbc=00 004b 16 reserved 0014 16 port p6 p6=00 004c 16 data bus buffer register 1 dbb1=00 0015 16 port p6 direction register p6d=00 004d 16 data bus buffer status register 1 dbbs1=00 0016 16 port p5 p5=00 004e 16 data bus buffer control register 1 dbbc1=00 0017 16 port p5 direction register p5d=00 004f 16 reserved 0018 16 port p4 p4=00 0050 16 usb address register usba=00 0019 16 port p4 direction register p4d=00 0051 16 usb power management register usbpm=00 001a 16 port p7 p7=00 0052 16 usb interrupt status register 1 usbis1=00 001b 16 port p7 direction register p7d=00 0053 16 usb interrupt status register 2 usbis2=00 001c 16 port p8 p8=00 0054 16 usb interrupt enable register 1 usbie1=ff 001d 16 port p8 direction register p8d=00 0055 16 usb interrupt enable register 2 usbie2=33 001e 16 reserved 0056 16 usb frame number register low usbsofl=00 001f 16 clock control register ccr=00 0057 16 usb frame number register high usbsofh=00 0020 16 timer xl txl=ff 0058 16 usb endpoint index usbindex=00 0021 16 timer xh txh=ff 0059 16 usb endpoint x in csr in_csr=00 0022 16 timer yl tyl=ff 005a 16 usb endpoint x out csr out_csr=00 0023 16 timer yh tyh=ff 005b 16 usb endpoint x in maxp in_maxp (endpoint dependent) 0024 16 timer 1 t1=ff 005c 16 usb endpoint x out maxp out_maxp (endpoint dependent) 0025 16 timer 2 t2=01 005d 16 usb endpoint x out wrt_cnt low wrt_cntl=00 0026 16 timer 3 t3=ff 005e 16 usb endpoint x out wrt_cnt high wrt_cnth=00 0027 16 timer x mode register txm=00 005f 16 reserved 0028 16 timer y mode register tym=00 0060 16 usb endpoint 0 fifo usbfifo0=n/a 0029 16 timer 123 mode register t123m=00 0061 16 usb endpoint 1 fifo usbfifo1=n/a 002a 16 sio shift register siosht=xx 0062 16 usb endpoint 2 fifo usbfifo2=n/a 002b 16 sio control register 1 siocon1=40 0063 16 usb endpoint 3 fifo usbfifo3=n/a 002c 16 sio control register 2 siocon2=18 0064 16 usb endpoint 4 fifo usbfifo4=n/a 002d 16 special count source generator1 scsg1=ff 0065 16 reserved 002e 16 special count source generator2 scsg2=ff 0066 16 reserved 002f 16 special count source mode register scsm=00 0067 16 reserved 0030 16 uart1 mode register u1mod=00 0068 16 reserved 0031 16 uart1 baud rate generator u1brg=xx 0069 16 reserved 0032 16 uart1 status register u1sts=03 006a 16 reserved 0033 16 uart1 control register u1con=00 006b 16 reserved 0034 16 uart1 transmit/receiver buffer 1 u1trb1=xx 006c 16 freq synthesizer control fsc=60 0035 16 uart1 transmit/receiver buffer 2 u1trb2=xx 006d 16 freq synthesizer multiply register 1 fsm1=ff 0036 16 uart1 rts control register u1rtsc=80 006e 16 freq synthesizer multiply register 2 fsm2=ff 0037 16 reserved 006f 16 freq synthesizer divide register fsd=ff
17 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.14 input and output ports table 1.5. input and output ports pin name input/ output i/o format non-port function related sfr?s ref. number p0 0 ? p0 7 port 0 input/output, individual bits cmos i/o port address bus cpu mode register fig. 1.15 p1 0 ? p1 7 port 1 input/output, individual bits cmos i/o port address bus cpu mode register fig. 1.15 p2 0 ? p2 7 port 2 input/output, individual bits cmos i/o port data bus cpu mode register fig. 1.15 p3 0 ? p3 7 port 3 input/output, individual bits cmos i/o port control signal i/o cpu mode register fig. 1.15 p4 0 expanded data memory access cpu mode register fig. 1.16 p4 1 external interrupt input (int0) interrupt edge selection register fig. 1.16 p4 2 external interrupt input (int1) interrupt edge selection register fig. 1.16 p4 3 external interrupt input (cntr0) timer x mode register fig. 1.16 p4 4 port 4 input/output, individual bits cmos i/o port external interrupt input (cntr1) timer y mode register fig. 1.16 p5 0 x cin cpu mode register fig. 1.17 p5 1 x cout or t out cpu mode register or t123 mode register fig. 1.17 p5 2 obf 0 output mbi interface fig. 1.17 p5 3 ibf 0 output mbi interface fig. 1.17 p5 4 s 0 input mbi interface fig. 1.17 p5 5 a 0 input mbi interface fig. 1.17 p5 6 r(e) input mbi interface fig. 1.17 p5 7 port 5 input/output, individual bits cmos i/o port w(r/w) input mbi interface fig. 1.17 p6 0 ? p6 7 port 6 input/output, individual bits cmos i/o port master cpu data bus mbi interface fig. 1.18 p7 0 sof output usb interface fig. 1.19 p7 1 hold cpu mode register fig. 1.19 p7 2 s 1 input mbi interface fig. 1.19 p7 3 ibf 1 output mbi interface fig. 1.19 p7 4 port 7 input/output, individual bits cmos i/o port obf 1 output mbi interface fig. 1.19 p8 0 utxd2/srdy uart mode register/sio mode register fig. 1.20 p8 1 urxd2/sclk uart mode register/sio mode register fig. 1.20 p8 2 cts2/stxd uart mode register/sio mode register fig. 1.21 p8 3 rts2/srxd uart mode register/sio mode register fig. 1.21 p8 4 utxd1 uart mode register fig. 1.21 p8 5 urxd1 uart mode register fig. 1.22 p8 6 cts1 uart mode register fig. 1.22 p8 7 port 8 input/output, individual bits cmos i/o port rts1 uart mode register fig. 1.22
18 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer direction register pull-up control d a t a b u s port latch key-on wake up input 1.14.1 i/o ports this device has 66 programmable i/o pins arranged as ports p0 0 to p8 7 . each port bit can be configured as input or output. to set the i/o port bit direction, write a ?1? to the corresponding direction register bit to select output mode, or write a ?0? to the direction register bit to select input mode. at reset, all of the direction registers are initialized to 00 16 , setting all of the i/o ports to input mode. if data is written to a pin and then read from that pin while it is in output mode, the data read is the value of the port latch rather than the value of the pin itself. therefore, if an external load changes the value of an output pin, the intended output value will still be read correctly. pins set to input mode are floating (pro- vided that the pull up resistors are not being used) to ensure that the value input to such a pin can be read accurately. in the case when data is written to a pin configured as an input, the data is written only to the port latch; the pin itself remains floating. most of the i/o ports are multiplexed with secondary functions. when a gpi/o is multiplexed with a sec- ond function, the control signal from the peripheral overrides the direction register. the multiplexing is briefly described below. the second function signals to and from the i/o ports are described in detail in their respective block?s description. 1.14.1.1 ports p0, p1, and p3 ports p0 and p1 act as the address bus (ab 0 -ab 15 ) in microprocessor and memory expansion modes. bits 0 and 3-7 of port p3 acts as control signals in microprocessor and memory expansion modes. 1.14.1.2 port p2 port p2 is an 8-bit general purpose i/o port when in single chip mode. in this mode, the port has key-on wake up circuitry which can be used to restart the chip externally from a wit or stp low power mode. this port also acts as the data bus during micropro- cessor and memory expansion modes. port p2 input level can be set to reduced vihl level or cmos level by bit 6 of the port control register (ptc). fig. 1.15. ports p0, p1, p2, p3 block diagram ports p0, p1, p3 port p2 direction register data bus port latch
19 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.14.1.3 port p4 port 4 is a 5-bit general purpose i/o port that can be configured to access special second functions. the port can be set up in any configuration in all three pro- cessor modes. port p4 0 this pin is multiplexed with the edma (extended data memory access) function. when the mcu is in memory expansion or microprocessor mode and cpmb4 is set to ?1?, this pin operates as the edma output as described in section 1.12.6. port p4 1 - p4 2 these pins are multiplexed with external interrupts 0 and 1 (int0 and int1). the external interrupt function is enabled by setting the bits to ?1? in the interrupt control register that correspond to int0 and int1. the interrupt polarity register can be configured to de- fine int0 and int1 as active high or low interrupts. see section 1.15.1 for more information on configur- ing interrupts. port p4 3 - p4 4 these pins are multiplexed with timer x and y func- tions for p4 3 and p4 4 respectively. the timer functions of the pins are independently defined by configuring the timer peripheral. p4 3 acts as timer x input pin for pulse width measurement mode and event counter mode or as timer x output pin for pulse output mode. p4 3 can also be used as an external in- terrupt (cntr0) when timer x in not in output mode. the polarity is selected in the timer x mode register. the external interrupt function is enabled by setting the bit to ?1? in the interrupt control register that corre- sponds to cntr0. see section 1.15.1 for more information on configuring interrupts. p4 4 acts as timer y input pin for pulse period mea- surement mode, pulse h-l measurement mode, and event counter mode or as timer y output pin for pulse output mode. p4 3 can also be used as an external in- terrupt (cntr1) when timer y in not in output mode. the polarity is selected in the timer y mode register. the external interrupt function is enabled by setting the bit to ?1? in the interrupt control register that corre- sponds to cntr1. see section 1.15.1 for more information on configuring interrupts. fig. 1.16. port p4 block diagram direction register d a t a b us port latch cpmb4 edma signal direction register data bus port latch cntr0, 1 input timer x, y output timer counter input enable pulse output mode enable direction register data bus port latch interrupt input port p4 0 port p4 1 and p4 2 port p4 3 and p4 4
20 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.14.1.4 port p5 port 5 is an 8-bit general purpose i/o port that can be configured to access special second functions. the port can be set up in any configuration in all three pro- cessor modes. port p5 0 this pin is multiplexed with the xc in clock input. when the xc in clock is activated, the pin?s i/o is dis- abled. port p5 1 this pin is multiplexed with the xc out clock output and the timer 1/2 pulse output. when the xc in clock is activated, the pin?s i/o is disabled. if xc in is not be- ing used as a system clock or xc out oscillation is dis- abled, the pin can be configured as the timer 1/2 pulse output pin. this feature is configured in the timer123 mode register as described in section 1.17. port p5 2 - p5 7 these pins are multiplexed with control pins for the bus interface control block. p5 2 acts as obf 0 output to a master cpu when dbbc00 is ?1?. p5 3 acts as ibf 0 output to a master cpu when dbbc01 is ?1?. p5 4 -p5 7 act as input control signals from a master cpu when dbbc06 is ?1?. the table featured in fig- ure 1.17 shows the bus interface control signal that corresponds to each pin. fig. 1.17. port p5 block diagram direction register data bus port latch cpma4 cpma4 cpma4 xc in input direction register data bus port latch t out enable bit timer 1/2 output direction register data bus port latch dbbc00 obf 0 direction register data bus port latch dbbc01 ibf 0 port 5 4 - p5 7 function pin function p5 4 s 0 p5 5 a 0 p5 6 r(e) p5 7 w(r/w) data bus port latch see table for function directi register dbbc06 dbbc06 on port p5 0 port p5 1 port 5 2 port p5 3 port p5 4 - p5 7
21 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.14.1.5 port p6 port p6 is an 8-bit general purpose i/o port that can be configured to access special second functions. the port acts as the data bus interface for the bus in- terface control block when dbbc06 is ?1?. the port can be set up in any configuration in all three proces- sor modes. fig. 1.18. port p6 block diagram data bus port latch mbi read status register 1 output buffer 1 a 1 input buffer 0 input buffer 1 status register 0 output buffer 0 a 0 s 0 mbi read s 1 mbi read s 0 mbi write s 1 mbi write mbi write s 0 s 1 direction register port p6
22 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.14.1.6 port p7 port p7 is a 5-bit general purpose i/o port that can be configured to access special second functions. port p7 0 this pin is multiplexed with the usb start of frame pulse (sof) output. when usbc6 is a ?1?, this pin outputs the usb sof. port p7 1 this pin is multiplexed with the hold function. when the mcu is in memory expansion or microprocessor mode and cpmb5 is set to ?1?. port p7 2 this pin is multiplexed with the s 1 input control signal from a master cpu. when dbbc17 is ?1?, the pin takes on the function of the s 1 input control signal. port p7 3 this pin is multiplexed with the ibf 1 output control signal for a master cpu and the hlda function. when dbbc11 and dbbc17 are ?1?, the pin takes on the function of the ibf 1 output control signal. when the mcu is in memory expansion or microprocessor mode, cpmb5 is set to ?1?, and the ibf 1 function is not enabled. port p7 4 this pin is multiplexed with the obf 1 control pin for the bus interface control block. p7 4 acts as obf 1 out- put to a master cpu when dbbc10 and dbbc17 are ?1?. fig. 1.19. port p7 block diagram direction register data bus port latch usbc6 sof data bus port latch direction register cpmb5 cpmb5 hold data bus port latch direction register dbbc17 dbbc17 s 1 direction register data bus port latch ibf 1 hlda dbbc17 dbbc11 cpmb5 direction register data bus port latch dbbc10 obf 1 dbbc17 port p7 0 port p7 1 port p7 2 port p7 3 port p7 4
23 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.14.5.7 port 8 port 8 is an 8-bit general purpose i/o port that can be configured to access special second functions. the port can be set up in any configuration in all three pro- cessor modes. port p8 0 this pin is multiplexed with the sio srdy signal and the uart2 txd signal. when uart2 is in transmit mode, the pin acts as the txd output signal. when the pin is not being used as the uart2 txd output and bit 4 of the sio control register 1 (siocon1) is a ?1?, the port acts as the sio srdy output signal. if during this function, the sio is configured in slave mode, this pin acts as a slave input from a master. see section 1.18 for more sio information. port p8 1 this pin is multiplexed with the sio sclk signal and the uart2 rxd signal. when uart2 is in receive mode, the pin acts as the rxd input signal. when the pin is not being used as the uart2 rxd input and bit 2 of the sio control register 1 (siocon1) is a ?1?, the port acts as the sio sclk signal. in this mode a ?1? in bit 6 of siocon1 configures the pin to output sclk whereas a ?0? configures the pin to input sclk. port p8 2 this pin is multiplexed with the sio srxd signal and the uart2 cts signal. when bit 5 of the uart2 control register (u2con) is a ?1?, the port acts as the cts input signal. when the pin is not being used as the uart2 cts input and bit 2 of the sio control reg- ister 2 (siocon2) is a ?1?, the port acts as the sio srxd input signal. port p8 3 this pin is multiplexed with the sio stxd signal and the uart2 rts signal. when bit 6 of the uart2 control register (u2con) is a ?1?, the port acts as the rts output signal. when the pin is not being used as the uart2 rts output and bit 3 of the sio control register 1 (siocon1) is a ?1?, the port acts as the sio stxd output signal. fig. 1.20. port p8 0 , p8 1, p8 2, p8 3 block diagram direction register data bus port latch sio ready output uart2 txd output uart2 transmit control bit srdy output selection bit sio slave control sio slave mode selection bit sio slave mode selection bit direction register data bus port latch sio clock output sio port selection bit sio clock selection bit sio clock input uart2 receive control bit uart2 receive control bit uart2 receive control bit uart2 rxd input sio clock selectio bit n direction register data bus port latch uart2 cts enable bit sio receive enable bit sio rxd input uart2 cts enable bit uart2 cts input direction register data bus port latch sio txd output uart2 rts output sio port selection bit transmit complete signal p-channel output disable bit uart2 rts enable bit port p8 0 port p8 1 port p8 2 port p8 3
24 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer port p8 4 this pin is multiplexed with the uart1 txd signal. when uart1 is in transmit mode, the pin acts as the txd output signal. port p8 5 this pin is multiplexed with the uart1 rxd signal. when uart1 is in receive mode, the pin acts as the rxd input signal. port p8 6 this pin is multiplexed with the uart1 cts signal. when bit 5 of the uart1 control register (u1con) is a ?1?, the port acts as the cts input signal. port p8 7 this pin is multiplexed with the uart1 rts signal. when bit 6 of the uart1 control register (u1con) is a ?1?, the port acts as the rts output signal. fig. 1.21. port p8 4 , p8 5 , p8 6 and p8 7 block diagram direction register data bus port latch uart1 transmit control bit uart1 txd utput o direction register data bus port latch uart1 receive control bit uart1 rxd input direction register data bus port latch uart1 cts enable bit uart1 cts input direction register data bus port latch uart1 rts enable bit uart1 rts output port p8 4 port p8 5 port p8 6 port p8 7
25 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer fig. 1.22. port control register (ptc) fig. 1.23. pull-up control register (pup2) ptc7 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 msb 7 lsb 0 address: 0010 16 access: r/w reset: 00 16 ptc6 ptc0 slew rate control bit ports p0-p3 (bit 0) 0: disabled 1: enabled ptc1 slew rate control bit port p4 (bit 1) 0: disabled 1: enabled ptc2 slew rate control bit port p5 (bit 2) 0: disabled 1: enabled ptc3 slew rate control bit port p6 (bit 3) 0: disabled 1: enabled ptc4 slew rate control bit port p7 (bit 4) 0: disabled 1: enabled ptc5 slew rate control bit port p8 (bit 5) 0: disabled 1: enabled ptc6 port p2 input level select bit (bit 6) 0 : reduced vihl level input 1 : cmos level input ptc7 master bus input level select bit (bit 7) 0 : cmos level input 1 : ttl level input pup2 7 pup2 5 pup2 4 pup2 3 pup2 2 pup2 1 pup2 0 msb 7 lsb 0 address: 0012 16 access: r/w reset: 00 16 pup2 6 pup2 0 pull-up control for port p2 (bit 0) 0: disabled 1: enabled pup2 1 pull-up control for port p2 (bit 1) 0: disabled 1: enabled pup2 2 pull-up control for port p2 (bit 2) 0: disabled 1: enabled pup2 3 pull-up control for port p2 (bit 3) 0: disabled 1: enabled pup2 4 pull-up control for port p2 (bit 4) 0: disabled 1: enabled pup2 5 pull-up control for port p2 (bit 5) 0: disabled 1: enabled pup2 6 pull-up control for port p2 (bit 6) 0: disabled 1: enabled pup2 7 pull-up control for port p2 (bit 7) 0: disabled 1: enabled 1.14.2 port control register (ptc) this device is equipped with a port control register to turn on and off the slew rate control and to control the input levels for port p2 and the mbi pins (see figure 1.22). 1.14.3 port p2 pull-up control register (pup2) this device is equipped with internal pull ups on port p2 that can be enabled by software. each bit of the pull-up control register controls a corresponding pin of port p2. the pull-up control register pulls up the port when the port is in input mode. the value of the pull- up control regsiter has no effect when the port is in output mode (see figure 1.23).
26 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.15 interrupt control unit this section details a specialized peripheral, the inter- rupt control unit (icu). this series supports a maximum of 23 maskable inter- rupts, one software interrupts, and one reset vector that is treated as a non-maskable interrupt. table 1.6 describes the interrupt registers. see table 1.7 for the interrupt sources, jump destination ad- dresses, interrupt priorities, and section references for the interrupt request sources. table 1.7. interrupt vector table 1.6. interrupt registers address description acronym and value at reset 0002 16 interrupt request register a ireqa=00 0003 16 interrupt request register b ireqb=00 0004 16 interrupt request register c ireqc=00 0005 16 interrupt control register a icona=00 0006 16 interrupt control register b iconb=00 0007 16 interrupt control register c iconc=00 0011 16 interrupt polarity selection register ipol=00 jump destination storage address (vector address) remarks priority interrupt high-order byte low-order byte reference 1 rsrv1 ffff fffe reserved for factory use 2 rsrv2 fffd fffc reserved for factory use 3 reset fffb fffa user reset (non-maskable) 4 usb fff9 fff8 usb function interrupt 0 lsb section 1.21.2.1 5 sof fff7 fff6 usb sof interrupt 1 section 1.21.2.2 6 int0 fff5 fff4 external interrupt 0 2 section 1.15.1 7 int1 fff3 fff2 external interrupt 1 3 section 1.15.1 8 dma1 fff1 fff0 dmac channel 0 interrupt 4 section 1.23 9 dma2 ffef ffee dmac channel 1 interrupt 5 section 1.23 10 u1rbf ffed ffec uart1 receiver buffer full 6 section 1.19.4.2 11 u1tx ffeb ffea uart1 transmit interrupt 7 msb ireqa & icona section 1.19.4.1 12 u1es ffe9 ffe8 uart1 error sum interrupt 0 lsb section 1.19.4.2 13 u2rbf ffe7 ffe6 uart2 receiver buffer full 1 section 1.19.4.2 14 u2tx ffe5 ffe4 uart2 transmit interrupt 2 section 1.19.4.1 15 u2es ffe3 ffe2 uart2 error sum interrupt 3 section 1.19.4.2 16 tx ffe1 ffe0 timer x interrupt 4 section 1.17 17 ty ffdf ffde timer y interrupt 5 section 1.17 18 t1 ffdd ffdc timer 1 interrupt 6 section 1.17 19 t2 ffdb ffda timer 2 interrupt 7 msb ireqb & iconb section 1.17 20 t3 ffd9 ffd8 timer 3 interrupt 0 lsb section 1.17 21 cntr0 ffd7 ffd6 external cntr0 interrupt 1 section 1.17.1.2 22 cntr1 ffd5 ffd4 external cntr1 interrupt 2 section 1.17.2 23 sio ffd3 ffd2 sio interrupt 3 section 1.18 24 ibf ffd1 ffd0 input buffer full interrupt 4 section 1.22 25 obe ffcf ffce output buffer empty interrupt 5 section 1.22 26 key ffcd ffcc key-on wake up 6 msb ireqc & iconc corresponding register assignment section 1.16 27 brk ffcb ffca brk instruction (non-maskable)
27 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.15.1 interrupt control each maskable interrupt has associated with it an in- terrupt request bit and an interrupt enable bit. these bits, along with the i flag, determine whether interrupt events can cause an interrupt service request to be generated. an interrupt request bit is set to ?1? when its corresponding interrupt event is activated. the bit is cleared to a ?0? when the interrupt is serviced or when a ?0? is written to the bit. the bit can not be set high by writing ?1? to it. each interrupt enable bit deter- mines whether the interrupt request bit it is paired with is seen when the interrupts are polled. when the inter- rupt enable bit is a ?0?, the interrupt request bit is not seen; and when the enable bit is a ?1?, the interrupt re- quest is seen. the interrupt request registers (ireq) for the 23 maskable interrupts are shown in figure 1.24, figure 1.25, and figure 1.26. the interrupt control registers (icon) for the 23 maskable interrupts are shown in figure 1.27, figure 1.28, and figure 1.29. fig. 1.26. interrupt request register c (ireqc) fig. 1.24. interrupt request register a (ireqa) fig. 1.25. interrupt request register b (ireqb) ira5 ira4 ira2 ira1 ira0 msb 7 lsb 0 ira3 ira7 ira6 ira 0 usb function interrupt request (bit 0) ira 1 usb sof interrupt request (bit 1) ira 2 external interrupt 0 request (bit 2) ira 3 external interrupt 1 request (bit 3) ira 4 dmac c hannel 0 interrupt request (bit 4) ira 5 dmac c hannel 1 interrupt request (bit 5) ira 6 uart1 r eceive buffer full interrupt request (bit 6) ira 7 uart1 tr ansmit interrupt request (bit 7) 0: no interrupt request issued 1: interrupt request issued address: 0002 16 access: r/w reset: 00 16 irb5 irb4 irb2 irb1 irb0 msb 7 lsb 0 irb3 irb7 irb6 irb 0 uart1 error sum interrupt request (bit 0) irb 1 uart2 receive buffer full interrupt request (bit 1) irb 2 uart2 transmit interrupt request (bit 2) irb 3 uart2 error sum interrupt request (bit 3) irb 4 timer x interrupt request (bit 4) irb 5 timer y interrupt request (bit 5) irb 6 timer 1 interrupt request (bit 6) irb 7 timer 2 interrupt request (bit 7) 0: no interrupt request issued 1: interrupt request issued address: 0003 16 access: r/w reset: 00 16 irc5 irc4 irc2 irc1 irc0 msb lsb 0 irc3 irc6 irc 0 timer 3 interrupt request (bit 0) irc 1 external cntr0 interrupt request (bit 1) irc 2 external cntr1 interrupt request (bit 2) irc 3 sio interrupt request (bit 3) irc 4 input buffer full interrupt request (bit 4) irc 5 output buffer empty interrupt request (bit 5) irc 6 key-on wake up interrupt request (bit 6) 0: no interrupt request issued 1: interrupt request issued bit 7 r eserved (read/write ?0?) address: 0004 16 access: r/w reset: 00 16 reserved
28 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer fig. 1.30. interrupt polarity register (ipol) fig. 1.29. interrupt control register c (iconc) fig. 1.28. interrupt control register b (iconb) fig. 1.27 interrupt control register a (icona) ica5 ica4 ica2 ica1 ica0 msb lsb 0 ica3 ica7 ica6 ica 0 usb function interrupt enable (bit 0) ica 1 usb sof interrupt enable (bit 1) ica 2 external interrupt 0 enable (bit 2) ica 3 external interrupt 1 enable (bit 3) ica 4 dmac c hannel 0 interrupt enable (bit 4) ica 5 dmac c hannel 1 interrupt enable (bit 5) ica 6 uart1 r eceive buffer full interrupt enable (bit 6) ica 7 uart1 tr ansmit interrupt enable (bit 7) 0: interrupt disable 1: interrupt enable address: 0005 16 access: r/w reset: 00 16 the interrupt polarity register allows the user to se- lect the edge that will trigger an external interrupt reserved reserved reserved int1 pol int0 pol msb 7 lsb 0 reserved reserved reserved address: 0011 16 access: r/w reset: 00 16 int0 pol int0 interrupt edge selection bit 0: falling edge selected 1: rising edge selected int1 pol int1 interrupt edge selection bit 0: falling edge selected 1: rising edge selected bits 2-7 reserved (read/write ?0?) request. the polarity register (ipol) for the external interrupts is shown in figure 1.30. icc 0 timer 3 interrupt enable (bit 0) icc 1 external cntr0 interrupt enable (bit 1) icc 2 external cntr1 interrupt enable (bit 2) icc 3 sio interrupt enable (bit 3) icc 4 input buffer full interrupt enable (bit 4) icc 5 output buffer empty interrupt enable (bit 5) icc 6 key-on wake up interrupt enable (bit 6) 0: interrupt disable 1: interrupt enable icc 7 r eserved (read/write ?0?) address: 0007 16 access: r/w reset: 00 16 icc5 icc4 icc2 icc1 icc0 msb 7 lsb 0 icc3 icc6 reserved icb5 icb4 icb2 icb1 icb0 msb 7 lsb 0 icb3 icb7 icb6 icb 0 uart1 error sum interrupt enable (bit 0) icb 1 uart2 receive buffer full interrupt enable (bit 1) icb 2 uart2 transmit interrupt enable (bit 2) icb 3 uart2 error sum interrupt enable (bit 3) icb 4 timer x interrupt enable (bit 4) icb 5 timer y interrupt enable (bit 5) icb 6 timer 1 interrupt enable ( bit 6) icb 7 timer 2 interrupt enable (bit 7) 0: interrupt disable 1: interrupt enable address: 0006 16 access: r/w reset: 00 16
29 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.16 key-on wake up this device contains a key-on wake up interrupt func- tion. the key-on wake up interrupt function is one way of returning from a power-down state caused by the stp or wit instructions. this interrupt is generated by applying low level to any pin of port p2. if a key matrix is connected as shown in figure 1.31, the mi- crocomputer can be returned to a normal state by pressing any one of the keys. key-on wake up is en- abled in single-chip mode only. fig. 1.31. port p2 with key-on wake up function key-on wake up interrupt request port p2 input read circuit port pxx l level output from arbitrary port xx p2 7 output p2 6 output p2 5 output p2 4 output p2 3 input p2 2 input p2 1 input p2 0 input off chip on chip pull p2 register bit 0 port p20 latch port p2 direction register bit 0 = "0" port p2 direction register bit 1 = "0" port p2 direction register bit 2 = "0" port p2 direction bit 7 = 1 port p2 direction register bit 6 = 1 port p2 direction register bit 5 = 1 port p2 direction register bit 4 = 1 port p2 direction register bit 3 = "0" port p21 latch port p22 latch port p23 latch port p24 latch port p25 latch port p26 latch port p27 latch register pull p2 register bit 1 pull p2 register bit 2 pull p2 register bit 3 pull p2 register bit 4 pull p2 register bit 5 pull p2 register bit 7 pull p2 register bit 6
30 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.17 timers this device has five built-in timers: timer x, timer y, timer 1, timer 2, and timer 3. the contents of the timer latch, corresponding to each timer, determine the divide ratio. the timers can be read or written at any time. however, the read and write operations on the high and low-order bytes of the 16-bit timers (timer x and y) must be performed in a specific order. the timers are all down count timers; when the count of a timer reaches 00 16 (0000 16 for timer x and y), an underflow occurs at the next count pulse and the contents of the corresponding timer reload latch are reloaded into the timer. when a timer underflows, the interrupt request bit corresponding to that timer is set to a ?1?. the divide ratio of a timer is given by 1/(n + 1), where n is the value written to the timer. when the stp in- struction is executed or reset is asserted, 01 16 is loaded into timer 2 and the timer 2 reload latch, and ff 16 is loaded into timer 1 and the timer 1 reload latch. figure 1.32 is a block diagram of the five timers. fig. 1.32. block diagram of timers x, y, 1, 2, and 3 timer x divider (1/ n ) timer y divider (1/ n ) n =8, 16, 32, 64 scsgclk txm2,1 tym3,2 1/8 timer xl latch(8) timer xl (8) timer xh latch(8) timer xh (8) txm0 timer x interrupt request cntr0 interrupt request 10 00 01 txm7 txm5,4 11 txm6 txm3 1 0 1 txm6 txm5, 4 = 01 0 1 q q t txm5,4= 01 rising edge detector tym5,4= 11 tym5,4= 01 or 11 timer yl latch(8) timer yl (8) timer yh latch(8) timer yh (8) tym0 tym7 tym5,4 00 01 11 10 0 tym6 tym= 1 & tym5, 4 = 00 1 tym6 0 1 q q t tym1= 11 and tym5,4 = 0 00 01 10 s tym5,4 11 timer y interrupt request cntr1 interrupt request 0 1 t123m5 t123m6= 1 t123m6= 1 timer 2 latch(8) timer 2 (8) t123m7 timer 2 timer 3 latch(8) timer3 (8) timer 3 1 timer 1 latch(8) timer 1 (8) t123m7 t123m3 t123m4 1 0 0 q q t s tout cntr1 cntr0 falling edge detector interrupt request interrupt request xc in /2 t123m2 0 1 0 t123m1 timer 1 interrupt request 0 1 t123m6 =1 q q t s t123m5 1 0 t123m0
31 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.17.1 timer x timer x is a 16-bit timer that has a 16-bit reload latch, and can be placed in one of four modes by setting bits txm4 and txm5 (bits 4 and 5 of the mode register, txm). the bit assignment of the txm is shown in fig- ure 1.33. 1.17.1.1 read and write method read and write operations on the high and low-order bytes of timer x must be performed in a specific or- der. ?write method when writing to the timer, the lower order byte is written first. this data is placed in a temporary reg- ister that is assigned the same address as timer xl. next, the higher order byte is written. when this is done, the data is placed in the timer xh reload latch and the low-order byte is transferred from its temporary register to the timer xl reload latch. at this point, if the timer x data write control bit (txm0) (bit 0) is ?0?, the value in the timer x reload latch is also loaded in timer x. if txm0 is ?0?, the data in the timer x reload latch is loaded in timer x after timer x underflows. ?read method when reading timer x, the high-order byte is real first. reading the high-order byte causes the values of timer xh and timer xl to be placed in temporary registers assigned the same addresses as timer xh and timer xl. the low-order byte of timer x is then read from its temporary register. this operation assures the correct reading of timer x while it is counting. 1.17.1.2 count stop control if the timer x count stop bit (txm7) (bit 7 of the txm) is set to a ?1?, timer x stops counting in all four modes. ?timer mode count source: /n (where n is 8, 16, 32, or 64) or scsgclk in this mode, each time the timer underflows, the cor- responding timer interrupt request bit is set to a ?1?, the contents of the timer latch are loaded into the timer, and the count down sequence begins again. fig. 1.33. timer x mode register (txm ) txm0 timer x data write control bit (bit 0) 0 : write data in latch and timer 1 : write data in latch only txm2,1 timer x frequency division ratio bits (bits 2,1) bit 2 bit 1 00: divided by 8 01: divided by 16 1 0 : divided by 32 11: divided by 64 txm3 timer x internal clock select (bit 3) 0: /n 1 : scsgclk (from chip special count source generation) txm5,4 timer x mode bits (bits 5,4) bit 5 bit 4 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1: pulse width measurement mode txm6 cntr0 polarity select bit (bit 6) 0 : for event counter mode, clocked by rising edge for pulse output mode, start from high level output for cntr0 interrupt request, falling edge active for pulse width measurement mode, measure high period 1 : for event counter mode, clocked on falling edge for pulse output mode, start from low level output for cntr0 interrupt request, rising edge active for pulse with measurement mode, measure low period txm7 timer x stop bit (bit 7) 0 : count start 1 : count stop txm7 txm5 txm4 txm3 txm2 txm1 txm0 msb 7 lsb 0 address: 0027 16 access: r/w reset: 00 16 txm6
32 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer ?pulse output mode count source: /n (where n is 8, 16, 32, or 64) or scsgclk each time the timer x underflows, the output of the cntr0 pin is inverted, and the corresponding timer x interrupt request bit is set to a ?1?. the repeated inversion of the cntr0 pin output produces a rect- angular waveform with a duty ratio of 50 percent. the initial level of the output is determined by the cntr0 polarity select bit (bit 6). when this bit is low, the out- put starts from a high level. when this bit is high, the output starts from a low level. ? event counter mode count source: cntr0 timer countdown is triggered by inputs to the cntr0 pin. each time a timer underflows, the corresponding timer interrupt request bit is set to a ?1?, the contents of the timer reload latch are loaded into the timer, and the countdown sequence begins again. the edge used to clock timer x is determined by the cntr0 polarity select bit (bit 6). ? pulse width measurement mode count source: /n (where n is 8, 16, 32, or 64) or scsgclk this mode measures either the high or low-pulse width of the signal on the cntr0 pin. the pulse width measured is determined by the cntr0 polarity se- lect bit (bit 6). when this bit is ?0?, the high pulse is measured. when this bit is ?1?, the low pulse is mea- sured. the timer counts down while the level on the cntr0 pin is the polarity selected by the cntr0 polarity se- lect bit. when the timer underflows, the timer x in- terrupt request bit is set to a ?1?, the contents of the timer reload latch are reloaded into the timer, and the timer continues counting down. each time the signal polarity switches to the inactive state, a cntr0 in- terrupt occurs indicating that the pulse width has been measured. the width of the measured pulse can be found by reading timer x during the cntr0 inter- rupt service routine.
33 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.17.2 timer y timer y is a 16-bit timer that has a 16-bit reload latch, and can be placed in any of four modes by setting tym4 and tym5 (bits 4 and 5) (see figure 1.34). the desired mode is selected by modifying the values of tym4 and tym5. 1.17.2.1 read and write method read and write operations on the high and low-order bytes of timer y must be performed in a specific or- der. ?write method when writing to the timer, the lower order byte is written first. this data is placed in a temporary reg- ister that is assigned the same address as timer yl. next, the high-order byte is written. then, the data is placed in the timer yh reload latch and the low-order byte is transferred from its temporary reg- ister to the timer yl reload latch. at this point, if the timer y data write control bit (tym0) (bit 0) is low, the value in the timer y reload latch is also loaded in timer y. if tym0 is ?1?, the data in the timer y reload latch is loaded in timer y after timer y underflows. fig. 1.34. timer y mode register (tym) ?read method when reading timer y, the high-order byte is read first. reading the high-order byte causes the values of timer yh and timer yl to be placed in temporary registers that are assigned the same addresses as timer yh and timer yl. the low-order byte of timer y is then read from its temporary register. this operation assures the correct reading of timer y while it is counting. 1.17.2.2 count stop control if the timer y count stop bit (tym7) (bit 7) is set to a ?1?, timer y stops counting in all four modes. ?timer mode count source: /n (where n is 8, 16, 32, or 64) in this mode, each time the timer underflows, the corresponding timer interrupt request bit is set to a ?1?, the contents of the timer latch are loaded into the timer, and the count down sequence begins again. in timer mode, the signal tyout can also be brought out on the cntr1 pin. this is controlled by tym1 (bit1). tym0 timer y data write control bit (bit 0) 0 : write data in latch and timer 1 : write data in latch only tym1 timer y output control bit (bit 1) 0 : tyout output disable 1 : tyout output enable tym3,2 timer y frequency division ratio bits (bit 3,2) bit 2 bit 1 00: divided by 8 01: divided by 16 10: divided by 32 11: divided by 64 tym5,4 timer y mode bits (bits 5,4) bit 2 bit 1 0 0 : timer mode 0 1: pulse period measurement mode 1 0 : event counter mode 1 1 : hl pulse width measurement mode (continu- ously measures high period and low period) tym6 cntr1 polarity select bit (bit 6) 0 : for event counter mode, clocked by rising edge for pulse period measurement mode, falling edge detection for cntr1 interrupt request, falling edge active for tyout, start on high output 1 : for event counter mode, clocked on falling edge for pulse period measurement mode, rising edge detection for cntr1 interrupt request, rising edge active for tyout, start on low output tym7 timer y stop bit (bit 7) 0 : count start 1 : count stop tym7 tym5 tym4 tym3 tym2 tym1 tym0 msb 7 lsb 0 address: 0028 16 access: r/w reset: 00 16 tym6
34 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer each time the timer y underflows, the output of the cntr1 pin is inverted, and the corresponding timer y interrupt request bit is set to a ?1?. the repeated in- version of the cntr1 pin output produces a rectangular waveform with a duty ratio of 50 percent. the initial level of the output is determined by the cntr1 polarity select bit (bit 6). when this bit is low, the output starts from a high level. when this bit is high, the output starts from a low level. ?pulse period measurement mode count source: /n (where n is 8, 16, 32, or 64). this mode measures the period of the event wave- form input to the cntr1 pin. ?cntr1 polarity select bit (tym6) = ?0? when the falling edge of an event waveform is de- tected on the cntr1 pin, the contents of timer y are stored in the temporary register that is as- signed the same address as timer y. simultaneously, the value in the timer y reload latch is transferred to timer y, and timer y contin- ues counting down. the falling edge of an event waveform also causes the cntr1 interrupt re- quest; therefore, the period of the event waveform from falling edge to falling edge is found by read- ing timer y in the cntr1 interrupt routine. the data read from timer y is the data previously stored in its temporary register. ?cntr1 polarity select bit (tym6) = ?1? when the rising edge of an event waveform is de- tected on the cntr1 pin, the contents of timer y are stored in the temporary register that is as- signed the same address as timer y. simultaneously, the value in the timer y reload latch is transferred to timer y, and timer y contin- ues counting down. the rising edge of an event waveform also causes the cntr1 interrupt request; therefore, the period of the event waveform from rising edge to rising edge is found by reading timer y in the cntr1 in- terrupt routine. the data read from timer y is the data previously stored in its temporary register. each time the timer underflows, the timer y interrupt request bit is set to a ?1?, the contents of the timer re- load latch are loaded into the timer, and the countdown sequence begins again. ?event counter mode count source: cntr1 timer countdown is triggered by input to the cntr1 pin. each time a timer underflows, the correspond- ing timer interrupt request bit is set to a ?1?, the contents of the timer reload latch are loaded into the timer, and the countdown sequence begins again. the edge used to clock timer y is determined by the cntr1 polarity select bit (bit 6). when these bits are ?0?s, the timers are clocked on the rising edge. when these bits are ?1?s, the timers are clocked on the falling edge ?hl pulse-width measurement mode count source: /n (where n is 8, 16, 32, or 64). this mode continuously measures both the logical high pulse width and the logical low pulse width of an event waveform input to the cntr1 pin. when the falling (or rising) edge of the event waveform is detected on the cntr1 pin, the contents of timer y are stored in the temporary register that is assigned the same address as timer y, regardless of the set- ting of the cntr1 polarity select bit. simultaneously, the value in the timer y reload latch is transferred to timer y, which continues counting down. the falling or rising edge of an event waveform causes the cntr1 interrupt request; therefore, the width of the event waveform from the falling or rising edge to ris- ing or falling edge is found by reading timer y in the cntr1 interrupt routine. the data read from timer y is the data previously stored in its temporary regis- ter. each time the timer underflows, the timer y interrupt request bit is set to a ?1?, the contents of the timer reload latch are loaded into the timer, and the count- down sequence begins again.
35 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.17.3 timer 1 timer 1 is an 8-bit timer with an 8-bit reload latch and has a pulse output option (see figure 1.35). t123m7 of timer123 mode register (t123m) is the timer 1 and 2 data write control bit. if t123m7 is ?1?, data written to timer 1 is placed only in the timer 1 reload latch. the latch value is loaded into timer 1 af- ter timer 1 underflows. if t123m7 is ?0?, the value written to timer 1 is placed in timer 1 and the timer 1 reload latch. at reset, t123m7 is set to a ?0?. the output signal tout is controlled by t123m5 and t123m6. t123m5 controls the polarity of tout. set- ting the bit t123m5 to ?1? causes tout to start at a low level, and clearing this bit to ?0? causes tout to start at a high level. setting t123m6 to ?1? enables tout, and clearing t123m6 to ?0? disables tout. ?timer mode count source: /8 or xcin/2 in timer mode, each time the timer underflows, the corresponding timer interrupt request bit is set to a ?1?, the contents of the timer latch are loaded into the timer, and the count down sequence begins again. ?pulse output mode count source: /8 or xcin/2 timer 1 pulse output mode is enabled by setting t123m6 to ?1? and t123m0 to a ?0?. each time the timer 1 underflows, the output of the tout pin is inverted, and the corresponding timer 1 interrupt request bit is set to a ?1?. the repeated inversion of the tout pin output produces a rectangular wave- form with a duty ratio of 50 percent. the initial level of the output is determined by the tout polarity se- lect bit (t123m5). when this bit is ?0?, the output starts from a high level. when this bit is ?1?, the out- put starts from a low level. fig. 1.35. timer 1, 2, 3 mode register (t123m) t123m0 tout source selection bit (bit 0) 0 : tout = timer 1 output 1 : tout = timer 2 output t123m1 timer 1 stop bit (bit 1) 0 : timer running 1 : timer stopped t123m2 timer 1 count source select bit (bit 2) 0: divided by 8 1 : xcin divided by 2 t123m3 timer 2 count source select bit (bit 3) 0 : timer 1 underflow signal 1: t123m4 timer 3 count source select bit (bit 5) 0 : timer 1 underflow signal 1: divided by 8 t123m5 tout output active edge selection bit (bit 5) 0 : start on high output 1 : start on low output t123m6 tout output control bit (bit 6) 0 : tout output disabled 1 : tout output enabled t123m7 timer 1 and 2 data write control bit (bit 7) 0 : write data in latch and timer 1 : write data in latch only t123m7 t123m5 t123m4 t123m3 t123m2 t123m1 t123m0 msb 7 lsb 0 address: 0029 16 access: r/w reset: 00 16 t123m6
36 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.17.4 timer 2 timer 2 is an 8-bit timer with an 8-bit reload latch (see figure 1.35). t123m7 (bit 7 of t123m) is the timer 1 and 2 data write control bit. if t123m7 is ?1?, data written to timer 2 is placed only in the timer 2 reload latch (see figure 1.32). the latch value is loaded into timer 2 after timer 2 underflows. if the t123m7 is ?0?, the value written to timer 2 is placed in timer 2 and the timer 2 reload latch. at reset, t123m2 is set to a ?0?. the timer 2 reload latch value is not affected by a change of the count source. however, because changing the count source may cause an inadvertent countdown of the timer, the timer should be rewritten when the count source is changed. ?timer mode count source: ?if t123m3 is ?0?, the timer 2 count source is the timer 1 underflow output. ?if t123m3 is ?1?, the timer 2 count source is . in timer mode, each time the timer underflows, the corresponding timer interrupt request bit is set to a ?1?, the contents of the timer latch are loaded into the timer, and the count down sequence begins again. ?pulse output mode count source: ?if t123m3 is ?0?, the timer 2 count source is the timer 1 underflow output. ?if t123m3 is ?1?, the timer 2 count source is . timer 2 pulse output mode is enabled by setting t123m6 to a ?1? and t123m0 to a ?1?. each time the timer 2 underflows, the output of the tout pin is inverted, and the corresponding timer 2 interrupt request bit is set to a ?1?. the repeated inversion of the tout pin output produces a rectangular wave- form with a duty ratio of 50 percent. the initial level of the output is determined by the tout polarity se- lect bit (t123m5). when this bit is ?0?, the output starts from a high level. when this bit is ?1?, the out- put starts from a low level. 1.17.5 timer 3 timer 3 is an 8-bit timer with an 8-bit reload latch (see figure 1.35). the timer 3 reload latch value is not af- fected by a change of the count source. because changing the count source may cause an inadvertent countdown of the timer, the timer should be rewritten whenever the count source is changed. ?timer mode count source: ?if t123m4 is ?0?, the timer 3 count source is the timer 1 underflow output. ?if t123m4 is ?1?, the count source is /8 in timer mode, each time the timer underflows, the corresponding timer interrupt request bit is set to a ?1?, the contents of the timer latch are loaded into the timer, and the count down sequence begins again. data written to timer 3 is always placed in timer 3 and the timer 3 reload latch.
37 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.18 serial i/o the serial i/o has the following main features: ? synchronous transmission or reception ? handshaking via srdy output signal ? 8-bit character length ? interrupt after transmission or reception ? internal clock (when serial i/o synchronous clock select bit is ?1?, internal clock source divided by 2, 4, 8, 16, 32, 64, 128, 256 can be selected). if bit 1 of sio control reg ister 2 is ?0?, internal clock source = ; if bit 1 of sio control register 2 is ?1?, internal clock source = scsgclk.) ? external clock (when sio synchronous clock select bit is ?1?, an external clock input from the sclk pin is selected). ?an spi compatible mode in which the txd and rxd pins function as mosi and miso pins, respectively. ?four (spi compatible) clock phase and polarity options. a block diagram of the clock synchronous sio is shown in figure 1.36. fig. 1.36. clock synchronous sio block diagram 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 1 scsel data bus synchronous circuit srd y p80 latch p81 latch sclk p83 latch stxd sio counter sio interrupt request sio shift register srxd 0 1 psel psel 0 1 rdysel external clock 0 scsgclk 1 0 0 1 clksel srd y spi slave divider spi scsel cpol cpha 01 spi slave spi slave selected
38 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.18.1 sio control registers (siocon) the serial i/o control register 1 controls various sio functions such as transfer direction and transfer clock divisor (see figure 1.37). all of this register?s bits can be read from and written to by software. at reset, this register is cleared to 00 16 . sio control register 2 determines the transfer clock phase and polarity, and also whether the sio is to function in spi compatible mode (see figure 1.38). all of this register?s bits can be read from and written to by software. at reset, this register is set to 18 16 . fig. 1.38. sio control register 2 (siocon2) fig. 1.37. sio control register 1 (siocon1) iscsel0-2 internal synchronization clock select bit (bits 2,1,0) bit 2 bit 1 bit 0 0 0 0 : internal clock divided by 2 0 0 1 : internal clock divided by 4 0 1 0 : internal clock divided by 8 0 1 1 : internal clock divided by 16 1 0 0 : internal clock divided by 32 1 0 1 : internal clock divided by 64 1 1 0 : internal clock divided by 128 1 1 1: internal clock divided by 256 psel sio port selection bit (bit 3) 0 : i/o port 1 : txd output, sclk function rdysel srdy output select bit (bit 4) 0 : i/o port 1 : srdy signal tdsel tr ansfer direction select bit (bit 5) 0 : lsb first 1 : msb first scsel synchronization clock select bit (bit 6) 0 : external clock 1 : internal clock ochcont txd output channel bit (bit 7) 0 : cmos output 1 : n-channel open drain output ochcont tdsel rdysel psel iscsel2 iscsel1 iscsel0 msb 7 lsb 0 address: 002b 16 access: r/w reset: 40 16 scsel spi spi mode selection bit (bit 0) 0 : normal sio mode 1 : spi compatibe mode clksel sio internal clock selection bit (bit 1) 0: 1: scsgclk rxdsel srxd input selection bit (bit 2) 0 : srxd input disabled 1 : srxd input enabled cpol clock polarity selection bit (bit 3) 0 : clock is low between transfers 1 : clock is high between transfers cpha clock phase selection bit (bit 4) 0 : data is captured on the leading edge of serial clock, changes on the following edge. 1 : data changes on the leading edge of serial clock, captured on the following edge. bit 5-7 reserved (r ead/write ?0?) reserved reserved cpha cpol rxdsel clksel sp1 msb 7 lsb 0 address: 002c 16 access: r/w reset: 18 16 reserved
39 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.18.2 sio normal operation an internal clock or an external clock can be selected as the synchronous clock. when the internal clock is chosen, dividers are built in to provide eight different clock selections. the start of a transfer is initiated by a write signal to the sio shift register (address 002a 16 ). the srdy signal then drops active low. on the negative edge of the transfer clock srdy returns high and the data is transmitted out the stxd pin. data is latched in from the srxd pin on the rising edge of the transfer clock. if an internal clock is se- lected, the stxd pin enters a high-impedance state after an 8-bit transfer is completed. if an external clock is selected, the contents of the serial i/o regis- ter continue to be shifted while the send/receive clock is being input. therefore, the clock needs to be con- trolled by the external source. also there is no stxd high-impedance function after data is transferred. regardless of whether an internal or external clock is selected, after an 8-bit transfer, the interrupt request bit is set. figure 1.39 shows the timing for the serial i/ o with the lsb-first option selected. synchronous clock transfer clock sio register receive enable sio output sio input write signal signal srdy interrupt request bit set see note note: when the internal clock is selected, the txd pin goes into high- impedance after the data is transferred. d0 d1 d2 d3 d4 d5 d6 d7 fig. 1.39. normal mode sio function timing (with lsb-first selected)
40 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.18.3 spi compatible operation setting the spi bit (bit 0 in siocon2) puts the sio in an spi compatible mode. the internal/external clock select bit (bit 6 in siocon1) determines whether the sio is an spi master or slave. if internal clock is se- lected the sio is a master, and if external clock is selected the sio is in slave mode. entering spi mode has the following effects on opera- tion: 1. the rxd pin functions as a miso (master in/slave out) pin. this means that when the spi is in slave mode transmit data will be output on this pin. in mas ter mode receive data is input on this pin. 2. the txd pin functions as a mosi (master out/slave in) pin. when the spi is in slave mode receive data is input on this pin. in master mode this pin drives the transmit data. 3. the srdy pin functions as a slave/chip select. if the spi is in slave mode, this pin functions as a slave se lect input. when configured as an spi master, the srdy pin functions as a chip select output. figure 1.40 shows the four possible spi clock-to-data relationships. the cpol and cpha bits (bits 3 and 4 in siocon2) are used to select the format. 1.18.3.1 spi slave mode when configured as an spi slave the sio does not initiate any serial transfers. all transfers are initiated by an external spi bus master. when the cpha (bit 4 in siocon2) is ?0? serial transfers begin with the fall- ing edge of the srdy input. for cpha = ?1? serial transfers begin when the sclk leaves its idle state (the clock idle state is defined by cpol, bit 3 in siocon2). if srdy is held high, the shift clock is inhibited, srxd (miso) is tri-stated, and the shift count is reset. if srdy is held low, then the shift operation is per- formed. the srdy input must be deasserted (brought high) between transfers; this resets the sio?s internal bit counter. when the sio is in spi slave mode, all transfers are initiated by an external spi bus master, not by the mcu. therefore, an application must implement some form of handshaking or synchronization to avoid writing to the sio shift register during a serial transfer. writing to the sio shift register during a transfer will corrupt the transfer in progress. sclk first bit last bit sclk sclk sclk srdy txd/rxd arrows indicate edge when data is captured cpol = 1 cpha = 1 cpol = 0 cpha = 1 cpol = 1 cpha = 0 cpol = 0 cpha 0 fig. 1.40. spi compatible transmission formats
41 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.19 uart this chip contains two identical uarts. each uart has the following main features: ? clock selection .................................. or scsgclk ? prescaler selection ............... x1/x8/x32/x256 divisions ............................................ (both and scsgclk) ? baud rate .......................................... (at = 12mhz) ......................... 1 1.4 bits/second-750 kbytes/second ? error detection ...................................... parity/framing/ ...................................................... overrun/error sum ? parity .................................................. odd/even/none ? stop bits ........................................................... 1 or 2 ? character length .................................... 7, 8, or 9 bits ? transmit/receive buffer .................................. 2 stages ...................................................... (double buffering) ? handshaking ............................... clear-to-send (cts) ............................................. request-to-send (rts) ? interrupt generation conditions ............. transmit buffer ..................................... empty or transmit complete ........................................................... receive buffer .................................................... receive error sum ? address ............... mode for multi-receiver environment the following descriptions apply to both uarts. the uart receives parallel data from the core or dmac, converts it into serial data, and transmits the results to the send data output terminal utxdx. the uart receives serial data from an external source through the receive data input urxdx, converts it into parallel data, and makes it available to the core or dmac. the uart can detect parity, overrun, and framing errors in the input stream and report the appro- priate status information. a double buffering configuration is used for the uart?s transmit and re- ceive operations. this double buffering is accomplished by the use of a transmit buffer and transmit shift register on the transmit side and the re- ceive buffer and receive shift register on the receive side. the uart supports an address mode for use in a multi-receiver environment where an address is sent before each message to designate which uart or uarts are to wake-up and receive the message. fig- ure 1.41 is a block diagram of the uart. it is valid for both uart1 and uart2. fig. 1.41. uart block diagram uart mode register uart control transmit data bus transmit uart status data bus uxmod register register uxsts uxcon buffer shift register st/stp/pa generator receive buffer register stop and start detect data format bit counter data format bit counter prescaler /1/8/32/256 clock set tx enable tx buffer empty tbe tis = "0" tis = "1" tcm transmit line to utxdx receive line from urxdx receive buffer full interrupt receive error interrupt rx complete rx status errors tx complete le 1,0; pen; stb le 1,0; pen; stb ps 1,0 clksel scsgclk transmit interrupt baud rate generator rx enable receive shift register to r tsx rts control register from ctsx rts_sel cts_sel data bus ___ ___
42 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer fig. 1.42. uart mode register (u1mod, u2mod) fig. 1.43. uart control register (u1con, u2con) le1 pen pmd stb ps1 ps0 clk msb 7 lsb 0 address: 0030 16 ,0038 16 access: r/w reset: 00 16 le0 1.19.1 uart mode register (uxmod) uxmod defines data formats and selects the clock to be used (see figure 1.42). 1.19.2 uart control register (uxcon) the uxcon specifies the initialization and enabling of a transmit/receive process (see figure 1.43). data can be read from and written to the control register. clk uart clock selection bit (bit 0) 0: 1: scsgclk ps1,0 internal clock prescaling selection bits (bits 2,1) bit 2 bit 1 0 0: division by 1 0 1: division by 8 1 0: division by 32 1 1: division by 256 stb stop bits selection bit (bit 3) 0: 1 1: 2 pmd parity selection bit (bit 4) 0: even 1: odd pen parity enable bit (bit 5) 0: off 1: on le1,0 uart character length selection bits (bits 7,6) bit 7 bit 6 0 0: 7 bits/character 0 1: 8 bits/character 1 0: 9 bits/character 1 1: reserved ame cts_sel tis rin tin ren ten msb 7 lsb 0 address: 0033 16 ,003b 16 access: r/w reset: 00 16 rts_sel ten transmission enable bit (bit 0) 0: disable the transmit process 1: enable the transmit process. if the transmit process is disabled (ten cleared) during transmission, the transmit will not stop until completed. ren receive enable bit (bit 1) 0: disable the receive process 1: enable the receive process. if the receive process is disabled (ren cleared) during reception, the receive will not stop until completed. tin transmission initialization bit (bit 2) 0: no action 1: resets the uart transmit status register bits as well as stopping the transmission operation. the ten bit must be set and the transmit buffer reloaded in order to transmit again. the tin is automatically reset one cycle after tin is set. rin receive initialization bit (bit 3) 0: no action 1: clears the uart receive status flags and the ren bit. if rin is set during receive in progress, receive operation is aborted. the rin bit is automatically reset one cycle after rin is set. tis transmit interrupt source selection bit (bit 4) 0: transmit interrupt occurs when the transmit buffer empty flag is set. 1: transmit interrupt occurs when the transmit complete flag is set. cts_sel clear-to send (cts) enable bit (bit 5) 0: cts function is disabled. p8 6 (or p8 2 ) is used as gpio pin. 1: cts function is enabled. p8 6 (or p8 2 ) is used as cts input. rts_sel request-to-send (rts) enable bit (bit 6) 0: rts function is disabled, p8 7 (or p8 3 ) is used as gpio pin. 1: rts function is enabled, p8 7 (or p8 3 ) is used as rts output. ame uart address mode enable bit (bit 7) 0: address mode disabled 1: address mode enabled
43 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.19.3 uart status register (uxsts) the uart status register (uxsts) reflects both the transmit and receive status (see figure 1.44). the sta- tus register is read only. the msb is always ?0? during a read operation. writing to this register has no effect. status flags are set and reset under the conditions in- dicated below. the setting and resetting of the transmit and receive status are not affected by trans- mit and receive enable flags. the setting and resetting of the receive error flags and receive buffer full flag dif- fers when uart address mode is enabled. these differences are described in section ?1.19.7 uart ad- dress mode?. 1.19.3.1 receive error sum flag the receive error sum flag (ser) is set when an overrun, framing, or parity error occurs after comple- tion of a receive operation. it is reset when the status register is read, the hard- ware reset is asserted, or the receiver is initialized by setting the receive initialization bit (rin). if the receive operation completes while the status register is being read, the status information is updated upon comple- tion of the status register read. 1.19.3.2 receive overrun flag the receive overrun flag (oer) is set if the previous data in the low-order byte of the receive buffer (uxtrb1) is not read before the current receive opera- tion is completed. it is also set if a receive error occurred for the previous data and the status register is not read before the current receive operation is com- pleted. this flag is reset when the status register is read. this flag is also reset when the hardware reset is asserted or the receiver is initialized by rin. if the re- ceive operation completes while the status register is being read, the status information is updated upon completion of the status register read. 1.19.3.3 receive framing error flag the receive framing error flag (fer) is set when the stop bit of the received data is ?0?. if the stop bit se- lection bit (stb, bit 3 of uxmod) is set, the flag is set if either of the two stop bits is a ?0?. this flag is reset when the status register is read, the hardware reset is asserted, or the receiver is initialized by rin. if the re- ceive operation completes while the status register is being read, the status information is updated upon completion of the status register read. 1.19.3.4 receive parity error flag the receive parity error flag (per) is set when the parity of received data and the parity selection bit (pmd, bit 4 of uxmod) are different. it is enabled only if the parity enable bit (pen, bit 5 of uxmod) is set. this flag is reset when the status register is read, the hardware reset is asserted, or the receiver is initialized by rin. if the receive operation completes while the status register is being read, the status information is updated upon completion of the status register read. 1.19.3.5 receive buffer full flag the receive buffer full flag (rbf) is set when the last stop bit of the data is received. it is not set when a receive error occurs. this flag is reset when the low- order byte of the receive buffer (uxtrb1) is read, the hardware reset is asserted, or the receive process is initialized by rin. if the receive operation completes while the status register is being read, the status infor- mation is updated upon completion of the status register read. 1.19.3.6 transmission complete flag in the case where no data is contained in the transmit buffer, the transmission complete flag (tcm) is set when the last bit in the transmit shift register is trans- mitted. in the case where the transmit buffer does contain data, the tcm flag is set when the last bit in the transmit shift register is transmitted if tbe is a ?0? or cts handshaking is enabled and ctsx is ?1?. the tcm flag is also set when the hardware reset is as- serted or when the transmitter is initialized by setting the transmit initialization bit (tin, bit 2 of uxcon). it is reset when a transmission operation begins. 1.19.3.7 transmission buffer empty flag the transmission buffer empty flag (tbe) is set when the contents of the transmit buffer are loaded into the transmit shift register. the tbe flag is also set when the hardware reset is asserted or when the transmitter is initialized by tin. it is reset when a write operation is performed to the low-order byte of the transmit buffer (uxtrb1).
44 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer reserved oer fer per rbf tbe tcm msb 7 lsb 0 address: 0032 16 ,003a 16 access: read only reset: 03 16 ser tcm transmission complete (transmission register empty) flag (bit 0) 0: data in transmission register 1: no data in transmission register tbe tx buffer empty flag (bit 1) 0: data in tx buffer 1: no data in the tx buffer rbf rx buffer full flag (bit 2) 0: no data in rx buffer 1: data in rx buffer per receive parity error flag (bit 3) 0: no parity error received 1: received framing error fer receive framing error flag (bit 4) 0: no framing error received 1: received framing error oer receive overrun flag (bit 5) 0: no overrun receive received 1: received overrun ser receive error sum flag (bit 6) 0: no error received 1: received error bit 7 reserved (read ?0?) fig. 1.44. uart status register (u1sts, u2sts) 1.19.4 transmit/receive methods 1.19.4.1 transmit method setup ?define the baud rate by writing a value from 0-255 into the uxbrg (see figure 1.45). ?set the transmission initialization bit (tin, bit 2 of uxcon), to ?1?. this will reset the transmit status to a value of 03 16 . ?select the interrupt source to be either tbe or tcm by clearing or setting the transmit interrupt source se- lection bit (tis, bit 4 of uxcon). ? configure the data format and clock selection by writ- ing the appropriate value to uxmod. ? set the clear-to-send enable bit (cts_sel, bit 5 of uxcon), if cts handshaking will be used. ?set the transmit enable bit (ten, bit 0 of uxcon), to ?1?. operation ?when data is written to the low-order byte of the trans- mit buffer (uxtrb1), tbe is cleared to ?0?. if 9-bit character length has been selected, the high-order byte of the transmit buffer (uxtrb2) should be written before the low-order byte (uxtrb1). ?if no data is being shifted out of the transmit shift reg- ister and cts handshaking is disabled, the data written to the transmit buffer is transferred to the transmit shift register and the tcm flag in uxsts is cleared to a ?0?. in addition, the tbe flag is set to a ?1?, signaling that the next byte of data can be written to the transmit buffer. if cts handshaking is enabled, the operation de- scribed above does not take place until ctsx is brought low. ?data from the transmit shift register is transmitted one bit at a time beginning with the start bit and ending with the stop bit. note that the lsb is transmitted first. ?if the ten bit is cleared to a ?0? while data is still be- ing transmitted, the transmitter will continue until the last bit is sent. this is also the case when cts hand- shaking is enabled and ctsx is brought back high during transmission. ?when the last bit is transmitted, the tcm flag is set to a ?1? if the transmit buffer is empty, ten is a ?0?, or cts handshaking is enabled and ctsx is ?1?. if the transmit buffer is not empty, ten is a ?1?, and cts handshaking is disabled or cts handshaking is en- abled and ctsx is low, the tcm flag is not set because transfer of the contents of the transmit buffer to the transmit shift register occurs immediately.
45 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.19.4.2 receive method set up ?define the baud rate by writing a value from 0-255 into uxbrg. ?set the receive initialization bit (rin, bit 3 in the uxcon), to "1". ?configure the data format and the clock selection by writing the appropriate value to uxmod. ?set the request-to-send enable bit (rts_sel, bit 6 of uxcon), if rts handshaking will be used. ?set the receive enable bit (ren, bit 1 in the uxcon), to "1". operation ?when a falling edge is detected on the urxdx pin, the value on the pin is sampled at the basic clock rate, which is 16 times faster than the baud rate. if the pin is low for at least two cycles of the basic clock, the start bit is detected. sampling is again performed three times in the approximate middle of the start bit. if two or more of the samples are low, the start bit is deemed valid. if two or more of the samples are not low, the start bit is invalidated and the uart again begins wait- ing for a falling edge on the urxdx pin. fig. 1.45. uart transmit operation waveform uxtrb1 uxbrg utxdx tbe start bit d0 stop bit start bit stop bit clock write tcm ?once a valid start bit has been detected, input data re- ceived through the urxdx pin is read one bit at a time, lsb first, into the receive shift register. as is the case with the start bit, three samples are taken in the ap- proximate middle of each data bit, the parity bit, and the stop bit(s). if two or more of the samples are low, a "0" is latched, and if two or more of the samples are high, a "0" is latched. ?when the number of bits specified by the data format has been received and the last stop bit is detected, the contents of the receive shift register are transferred to the receive buffer and the receive buffer full flag in the uxsts is set to a "1", if a receive error has not oc- curred (see figure 1.46). the rbf interrupt request is also generated at this time if a receive error has not oc- curred. however, if a receive error did occur, the appropriate error flags are set and the receive error sum (ser) interrupt request is generated at this time. ?when the low-order byte of the receive buffer (uxtrb1) is read, the receive buffer full flag is cleared, and the receive buffer is now ready for the next byte. if 9-bit character length has been selected, the high-order byte of the receive buffer (uxtrb2) should be read before reading the low-order byte (uxtrb1).
46 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer fig. 1.46. uart receive operation waveforms uxbrg urxdx rbf start bit d0 stop bit start bit clock d0 edge detection 2-of-3 sampling 2-of-3 sampling 2-of-3 sampling 2-of-3 sampling 2-of-3 sampling edg detection uxtrb1 read programmable delay cts (input) txd (output) rxd (input) rts (output) data stop start data start data in both examples, the transmit and receive have already been enabled fig. 1.48. uxrtsc register fig. 1.47. ctsx and rtsx timing examples rts3 rts1 reserved msb 7 lsb 0 address: 0036 16 ,003e 16 access: r/w reset: 80 16 rts2 0-3 reserved (read/write ?0?) rts3:0 rts assertion delay count 3:0 (bits 7, 6, 5, 4) 0000: no delay, rts asserts immediately after receive operation completes 0001: rts asserts 8 bit-times after receive operation completes 0010: rts asserts 16 bit-times after receive operation completes 0011: rts asserts 24 bit-times after receive operation completes 1000: rts asserts 64 bit-times after receive operation completes 1110: rts asserts 112 bit-times after receive operation completes 1111: rts asserts 120 bit-times after receive operation completes rts0 reserved reserved reserved
47 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.19.5 interrupts the transmit and receive interrupts are generated un- der the conditions described below. the generation of the receive interrupts differs when uart address mode is enabled. 1.19.5.1 transmit interrupts the uart generates a transmit interrupt to the cpu core. the source of the transmit interrupt is select- able by setting tis. ?if tis = ?0?, the transmit interrupt is generated when the transmit buffer register becomes empty (that is, when tbe flag set). ?if tis = ?1?, the transmit interrupt is generated after the last bit is sent out of the transmit shift register and no data has been written to the transmit buffer or cts handshaking is enabled and ctsx is high (that is, when tcm flag set). 1.19.5.2 receive interrupts the uart generates the receive buffer full (rbf) and receive error sum (ser) interrupts to the cpu core when receiving. ?the rbf interrupt is generated when a receive opera- tion completes and a receive error is not generated. ?the ser interrupt is generated when an overrun, fram- ing or parity error occurs. 1.19.6 clear-to send (ctsx) and request-to-send (rtsx) signals the uart, as a transmitter, can be configured to rec- ognize the clear-to-send (ctsx) input as a handshaking signal. as a receiver, the uart can be configured to generate the request-to-send (rtsx) handshaking signal. 1.19.6.1 clear-to-send (ctsx) input cts handshaking is enabled by setting the clear-to- send enable bit (cts_sel, bit 5 of uxcon) to a ?1?. if cts handshaking is enabled, when ten is a ?1? and the low-order byte of the transmit buffer (uxtrb1) is loaded, the uart begins the transmission process when the ctsx pin is asserted (low input). after begin- ning a send operation, the uart does not stop sending until the transmission is completed, even if ctsx is deasserted (high input). if ten is cleared to ?0?, the uart will not stop transmitting and the port pins will remain under the control of the uart until the end of the transmission. if cts handshaking is disabled and ten is a ?1?, the uart begins the trans- mission process as soon as data is available in the low-order byte of the transmit buffer (uxtrb1). figure 1.47 shows a timing example for ctsx. 1.19.6.2 request-to-send (rtsx) output rts handshaking is enabled by setting the request- to-send enable bit (rts_sel, bit 6 of uxcon) to a ?1?. when rts handshaking is enabled, the uart drives the rtsx output low or high based on the fol- lowing conditions: ?assertion conditions (driven low): ?the receive enable bit (ren) is set to a ?1?. ?receive operation has completed with the reception of the last stop bit, ren is still a ?1?, and the program- mable assertion delay has expired. ?de-assertion conditions (driven high): ?a valid start bit is detected and ren is a ?1?. ?ren is cleared to a ?0? before a receive operation is in progress. ?receive operation has completed and ren is a ?0?. ?uart receiver is initialized (rin is set to a ?1?). the delay time from the reception of the last stop bit to the re-assertion of rtsx is programmable. the amount of delay is selected by setting the rts asser- tion delay count bits (rts 3~0, bits 3 to 0 of uxrtsc) (see figure 1.48 ). the time can be from no delay to 120 bit-times, with the delay beginning from the middle of the last stop bit. if a start bit is detected before the assertion delay has expired, the delay countdown is stopped and the rtsx pin remains high. a full assertion delay countdown will begin again once the last stop bit of the incoming data has been re- ceived. see figure 1.47 for a timing example for rtsx.
48 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.19.7 uart address mode the uart address mode is intended for use in a multi-receiver environment where an address is sent before each message to designate which uart or uarts are to wake-up and receive the message. an address is identified by the msb of the incoming data byte being a ?1?. the bit is ?0? for non-address data. uart address mode can be used in either 8-bit or 9- bit character length mode. the character length is chosen by writing the appropriate values to the uart character length selection bits (le1,0). uart address mode is enabled by setting the uart address mode enable bit (ame) to ?1?. when uart address mode is enabled, the msb of a newly re- ceived byte of data (that is either 8 or 9 bits in length) is examined if a valid stop bit is detected and a parity error has not occurred (if parity is enabled). if the msb is ?1?, then the receive buffer full interrupt and flag are set and ame is automatically cleared, disabling uart address mode. if the msb is ?0?, then the receive buffer full interrupt is not set. however, the rbf flag is still set for this case. if a valid stop bit is not detected or a parity error has occurred, neither the receive buffer full flag nor interrupt is set and the msb of the data is not examined. instead, either the framing error or par- ity error flag is set, the error sum flag is set, and the error sum interrupt is set. while in uart address mode, the generation of over- run errors is disabled after the first byte of data is received. therefore, when non-address data is re- ceived without errors while in the uart address mode, it is not necessary to read the uart receive buffer prior to the reception of the next byte of data. also, if a framing or parity error occurs while in uart address mode, it is not necessary to read the uxsts prior to the reception of the next byte of data. however, an overrun error will occur if an address byte is received and the uart receive buffer is not read before a new byte of data is received. this is the case because the uart address mode was automatically disabled when the address byte was received. also, an overrun error will occur for the first byte received after uart address mode is enabled if the preceding byte received did not generate an error and the uart receive buffer was not read, or the preceding byte did generate an error and uxsts was not read.
49 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer fig. 1.51. special count source mode register (scsm) 1.20 special count source generator this device has a built-in special count source genera- tor. it cons ists of two 8-bit timers: scsg1, and scsg2 (see figure 1.49). the contents of the timer latch, corresponding to each timer, determine the di- vide ratio. the timers can be written to at any time. the output of the special count source generator can be a clock source for timer x, sio and the two uarts. 1.20.1 scsg operation the scsg1 and scsg2 are both down count timers. when the count of a timer reaches 00 16 , an underflow occurs at the next count pulse and the contents of the corresponding timer reload latch are loaded into the timer. for the count operation for scsg1 with the data write mode set to write to the latch only (see figure 1.50). a memory map and the initial values after reset of the timers and timer reload latches are detailed above. the divide ratio of each timer is given by 1/(n + 1), where n is the value written to the timer. the output of the first timer (scsg1) is effectively anded with the original clock ( ) to provide a count source for the second timer (scsg2). this results in a count source of n/(n + 1) being fed to scsg2. the output of the scsg is a clock, scsgclk. the frequency is calculated as follows: where scsg1 is the value written to scsg1 and scsg2 is the value written to scsg2. see figure 1.51 for the special count source mode register. scsgm0 scsg1 data write control bit (bit 0) 0 : write data in latch and timer 1 : write data in latch only scsgm1 scsg1 count stop bit (bit 1) 0 : count start 1 : count stop scsgm2 scsg2 data write control bit (bit 2) 0 : write data in latch an timer 1 : write data in latch only scsgm3 scsgclk output control bit (bit 3) 0 : scsgclk output disabled (scsg1 and scsg2 off) 1 : scsgclk output enable. bits 4-7 reserved (read/write ?0?) reserved reserved reserved scsgm2 scsgm1 scsgm0 msb 7 lsb 0 address: 002f 16 access: r/w reset: 00 16 reserved scsgm3 scsgm1 scsgm3 scsg1 reload latch (8) scsg1 (8) scsgm1 scsgm1 scsgm3 scsgm0 scsgm2 scsg2 reload latch (8) scsgm3 scsgclk (to uarts, timer x and sio) scsg (8) count source scsg1 contents scsg1 underflow scsg1 latch contents scsg1 reload latch contents loaded int scsg1 10 nn -1 1 0 m m-1 n m fig. 1.49. scsg block diagram fig. 1.50. timer count operation for scsg1 scsc1+1 scsg2+1 scsgclk = ? scsg1 ? 1
50 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.21 universal serial bus the universal serial bus (usb) has the following fea- tures: ?complete usb specification (version 1.1) compatibility ?error handling capabilities ?fifos: ?endpoint 0: in 16-byte out 16-byte ?endpoint 1: in 512-byte out 800-byte ?endpoint 2: in 32-byte out 32-byte ?endpoint 3: in 16-byte out 16-byte ?endpoint 4: in 16-byte out 16-byte ?five independent in endpoints ?five independent out endpoints ?complete device configuration ?supports all device commands ?supports full-speed functions ?support of all usb transfer types: ?isochronous ?bulk ?control ?interrupt ?suspend/resume operation ?on-chip usb transceiver with voltage converter ?start-of-frame interrupt and output pin 1.21.1 usb function control unit (usbfcu) the implementation of the usb by this device is ac- complished chiefly through the device?s usb function control unit. the function control unit?s overall pur- pose is to handle the usb packet protocol layer. the function control unit notifies the mcu that a valid to- ken has been received. when this occurs, the data portion of the token is routed to the appropriate fifo. the mcu transfers the data to, or from, the host by interacting with that endpoint?s fifo and csr regis- ter (see figure 1.51). the usb function control unit is composed of five sections: ?serial interface engine (sie) ?generic function interface (gfi) ?serial engine interface unit (siu) ?microcontroller interface (mci) ?usb transceiver 1.21.1.1 serial interface engine the sie interfaces to the usb serial data and handles deserialization/serialization of data, nrzi encoding/ decoding, clock extraction, crc generation and checking, bit stuffing, and other specifications pertain- ing to the usb protocol such as handling inter-packet time-outs and pid decoding 1. 1.21.1.2 generic function interface the gfi handles all usb standard requests from the host through the control endpoint (endpoint 0), and handles bulk, isochronous and interrupt transfers through endpoints 1-4. the gfi handles read pointer reversal for re-transmission of the current data set; write pointer reversal for re-reception of the last data set, and data toggle synchronization. 1.21.1.3 serial engine interface unit the siu block decodes the address and endpoint fields from the usb host. 1.21.1.4 microcontroller interface unit the mci block handles the microcontroller interface and performs address decoding and synchronization of control signals. 1.21.1.5 usb transceiver the usb transceiver, designed to interface with the physical layer of the usb, is compliant with the usb specification (version 1.1) for high speed devices. it consists of two 6-ohm drivers, a receiver, and schmitt triggers for single-ended receive signals. cpu mci siu gfi fifos sie transceiver d + d - fig. 1.51. usb function control unit block diagram
51 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.21.2 usb interrupts there are two types of usb interrupts in this device. usb function (including overrun/underrun, reset, sus- pend and resume) interrupt, which is used to control the flow of data. the second type is start-of-frame (sof) interrupt, which is used to monitor the transfer of isochronous (iso) data. 1.21.2.1 usb function interrupts endpoints 1-4 each have two interrupt status flags as- sociated with them to control data transfer or to report a stall/under_run/over_run condition. the usb endpoint x out interrupt status flag is set when the usb fcu successfully receives a packet of data, or the usb fcu sets the force_stall bit or the over_run bit of the endpoint x out csr. the usb endpoint x in interrupt status flag is set when the usb fcu successfully sends a packet of data or sets the under_run bit of the endpoint x in csr. endpoint 0 (the control endpoint) has one interrupt status bit associated with it to control data transfer or report a stall condition. the usb endpoint 0 inter- rupt status flag is set when the usb fcu successfully receives/sends a packet of data, sets the setup_end bit or the force_stall bit, or clears the data_end bit in the endpoint 0 in csr. each endpoint interrupt is enabled by setting the corre- sponding bit in the usb interrupt enable register 1 and 2 (see figure 1.57 and figure 1.58). the usb in- terrupt status register 1 and 2, shown in figure 1.55 and figure 1.56, are used to indicate pending inter- rupts for a given endpoint. the usb fcu sets the interrupt status bits. the cpu writes a ?1? to clear the corresponding status bit. by writing back the same value it read, the cpu will clear all the existing inter- rupts. the cpu must read then write both status registers, writing status register 1 first and status reg- ister 2 second to guarantee proper operation. the suspend signaling interrupt status flag is set if the usb fcu does not detect any bus activity on d+/ d- for at least 3ms. the resume signaling interrupt status flag is set when a usb fcu is in the suspend state and detects non-idle signaling on d+/d-. there is an interrupt enable bit for the suspend interrupt (bit 7 of interrupt enable register 2), but not one for the resume interrupt. the resume interrupt is always en- abled. the usb reset interrupt status flag is set if the usb fcu sees a se0 present on d+/d- for at least 2.5ms. when this bit is set, all usb internal registers (except for this bit) are reset to their default values. this bit is cleared by the cpu writing a ?1? to it. when the cpu detects a usb reset interrupt, it needs to re-initialize the usb fcu in order for it to accept packets from the host. the usb reset interrupt is always enabled. the overrun/underrun interrupt status flag is set (applicable to endpoints used for isochronous data transfer) when an overrun condition occurs in an end- point (cpu is too slow to unload the data from the fifo), or when an underrun condition occurs in an endpoint (cpu is too slow to load the data to the fifo). the usb function interrupt (sum of all individual function interrupts) is enabled by setting bit 0 of inter- rupt control register a (icona) to a ?1?. 1.21.2.2 usb sof interrupt the usb sof (start-of-frame) interrupt is used to control the transfer of isochronous data. the usb fcu generates a start-of-frame interrupt when a start-of-frame packet is received. the usb sof inter- rupt is enabled by setting bit 1 of icona to a ?1?. 1.21.3 usb endpoint fifos the usb fcu has an in (transmit) fifo and an out (receive) fifo for each endpoint. each endpoint (ex- cept endpoint 0) can be configured to support both single packet mode (only a single data packet is al- lowed to reside in the endpoint?s fifo) or dual packet mode (up to two data packets are allowed to reside in the endpoint?s fifo), which provides support for back-to-back transmission or back-to-back reception. the mode configuration is automatically set by the maxp value. when maxp > 1/2 of the endpoint?s fifo size, single packet mode is set. when maxp <= 1/2 of the endpoint?s fifo size, dual packet mode is set. throughout this specification, the terms ?in fifo? and ?out fifo? refer to the fifos associated with the current endpoint as specified by the endpoint in- dex register. in the event of a bad transmission/reception, the usb fcu handles all the read/write pointer reversal and data set management tasks when it is applicable.
52 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.21.3.1 in (transmit) fifos the cpu/dma writes data to the endpoint?s in fifo location specified by the fifo write pointer, which au- tomatically increments by ?1? after a write. the cpu/ dma should only write data to the in fifo if the in_pkt_rdy bit of the in csr is a ?0?. ? endpoint 0 in fifo operation: the cpu writes a ?1? to the in_pkt_rdy bit after it finishes writing a packet of data to the in fifo. the usb fcu clears the in_pkt_rdy bit after the packet has been successfully transmitted to the host (ack is received from the host) or the setup_end bit of the in csr is set to a ?1?. ? endpoint 1-4 in fifo operation when auto_set (bit 7 of in csr) = ?0?: maxp > 1/2 of the in fifo size: the cpu writes a ?1? to the in_pkt_rdy bit after the cpu/dmac finishes writing a packet of data to the in fifo. the usb fcu clears the in_pkt_rdy bit after the packet has been successfully transmitted to the host (ack is received from the host). maxp <= 1/2 of the in fifo size: the cpu writes a ?1? to the in_pkt_rdy bit after the cpu/dmac finishes writing a packet of data to the in fifo. the usb fcu clears the in_pkt_rdy bit as soon as the in fifo is ready to accept another data packet. (the fifo can hold up to two data packets at the same time in this configuration for back-to-back transmission). since the set and the clear opera- tions could be as fast as 83ns (one 12mhz clock period) apart from each other, the set may be trans- parent to the user. ? endpoint 1-4 in fifo operation when auto_set (bit 7 of in csr) = ?1?: maxp > 1/2 of the in fifo size: when the number of bytes of data equal to the maxp (maximum packet size) is written to the in fifo by the cpu/ dmac, the usb fcu sets the in_pkt_rdy bit to a ?1? automatically. the usb fcu clears the in_pkt_rdy bit after the packet has been suc- cessfully transmitted to the host (ack is received from the host). maxp <= 1/2 of the in fifo size: when the num- ber of bytes of data equal to the maxp (maximum packet size) is written to the in fifo by the cpu/ dmac, the usb fcu sets the in_pkt_rdy bit to a ?1? automatically. the usb fcu clears the in_pkt_rdy bit as soon as the in fifo is ready to accept another data packet. (the fifo can hold up to two data packets at the same time in this con- figuration for back-to-back transmission). since the set and the clear operations could be as fast as 83ns (one 12mhz clock period) apart from each other, the set may be transparent to the user. a software or a hardware flush causes the usb fcu to act as if a packet has been successfully transmit- ted out to the host. if there is one packet in the in fifo, a flush will cause the in fifo to be empty. if there are two packets in the in fifo, a flush will cause the older packet to be flushed out from the in fifo. a flush will also update the in fifo status bits in_pkt_rdy and tx_not_empty. the status of endpoint 1-4 in fifos for both of the above cases can be obtained from the in csr of the corresponding in fifo as shown in table 1.8. table 1.8. endpoint 1_4 in fifo status ? interrupt endpoints: any endpoint can be used for interrupt transfers. for normal interrupt transfers, the interrupt transactions behave the same as bulk transactions, i.e.; no special setting is required. the in endpoints may also be used to communicate rate feedback information for certain types of isochronous functions. this is done by setting the intpt bit in the in csr register of the corresponding endpoint. when the intpt bit is set, the data toggle bits will be changed after each packet is sent to the host without regard to the presence or type of handshake packet. 0 01 1 1 in_pkt_rdy tx_not_empty tx fifo status 1 0 0 invalid two data packets in tx fifo if maxp <= 1/2 of the fifo size or one data packet in tx fifo if maxp > 1/2 of the fifo size no data packet in tx fifo one data packet in tx fifo if maxp <= 1/2 of the fifo size invalid if maxp > 1/2 of the fifo size/
53 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer the following outlines the operation sequence for an in endpoint used to communicate rate feedback infor- mation: 1. set maxp > 1/2 of the endpoint?s fifo size 2. set the intpt bit of the in csr 3. flush the old data in the fifo 4. load interrupt status information and set the in_pkt_rdy bit in the in csr 5. repeat steps 3 and 4 for all subsequent interrupt status updates. in real applications, if an interrupt endpoint is used for rate feedback, the function always has data to send back to the host, even if that data conveys that every- thing is ?fine?. therefore the device never naks an in token from the host. the device always sends out the data in the fifo in response to an in token irrespec- tive of the in_pkt_rdy bit. 1.21.3.2 out (receive) fifos the usb fcu writes data to the endpoint?s out fifo location specified by the fifo write pointer, which automatically increments by one after a write. when the usb fcu has successfully received a data packet, it sets the out_pkt_rdy bit to a ?1? in the out csr. the cpu/dmac should only read data from the out fifo if the out_pkt_rdy bit of the out csr is a ?1?, with the exception of endpoint 1 (see detailed description below). ? endpoint 0 out fifo operation: the usb fcu sets the out_pkt_rdy bit to a ?1? after it has successfully received a packet of data from the host. the cpu sets bit serviced_out_pkt_rdy to a ?1? to clear the out_pkt_rdy bit after the packet of data has been unloaded from the out fifo by the cpu. ? endpoint 1-4 out fifo operation when auto_clr (bit 7 of out csr) = ?0?: maxp > 1/2 of the out fifo size: the usb fcu sets the out_pkt_rdy bit to a ?1? after it has suc- cessfully received a packet of data from the host. the cpu writes a ?0? to the out_pkt_rdy bit af- ter the packet of data has been unloaded from the out fifo by the cpu/dmac. maxp <= 1/2 of the out fifo size: the usb fcu sets the out_pkt_rdy bit to a ?1? after it has successfully received a packet of data from the host. the cpu writes a ?0? to the out_pkt_rdy bit after the packet of data has been unloaded from the out fifo by the cpu/dmac. in this configura- tion, the fifo can hold up to two data packets at the same time for back-to-back reception. there- fore, the out_pkt_rdy bit will remain set after the cpu writes a ?0? to it if there is another packet in the out fifo. ? endpoint 1-4 out fifo operation when auto_clr (bit 7 of out csr) = ?1?: maxp > 1/2 of the out fifo size: the usb fcu sets the out_pkt_rdy bit to a ?1? after it has suc- cessfully received a packet of data from the host. the usb fcu clears the out_pkt_rdy bit to a ?0? automatically when the number of bytes of data equal to the maxp (maximum packet size) have been unloaded from the out fifo by the cpu/ dmac. maxp <= 1/2 of the out fifo size: the usb fcu sets the out_pkt_rdy bit to a ?1? after it has successfully received a packet of data from the host. the usb fcu clears the out_pkt_rdy bit to a ?0? automatically when the number of bytes of data equal to the maxp (maximum packet size) have been unloaded from the out fifo by the cpu/dmac. in this configuration, the fifo can hold up to two data packets at the same time for back-to-back reception. therefore, the out_pkt_rdy bit will remain set after one packet (size equal to maxp) of data has been unloaded if there is another packet in the out fifo. a software flush causes the usb fcu to act as if a packet has been unloaded from the out fifo. if there is one packet in the out fifo, a flush will cause the out fifo to be empty. if there are two packets in the out fifo, a flush will cause the older packet to be flushed out from the out fifo. special case for out endpoint 1: in addition to the out fifo operations described above, the dmac can also start unloading the out fifo as soon as there is data in it (byte-by-byte transfer). this feature should only be used with iso transfers. see dmac section for details.
54 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.21.4 usb special function registers the mcu controls usb operation through the use of special function registers (sfr). this section de- scribes in detail each usb related sfr. certain usb sfrs are endpoint-indexed: the control & status registers (in csr and out csr), the maximum packet size registers (in maxp and out maxp), and the write count registers (out wrt cnt). to access each endpoint-indexed sfr, the target end- point number should be written to the endpoint index register first. the lower 3 bits (epindx2:0) of the endpoint index register are used for endpoint selec- tion. note: each endpoint?s fifo register is not end- point-indexed. some usb special function registers have a mix of read/write, read only, and write-only register bits. ad- ditionally, the bits may be configured to allow the user to write only a ?0? or a ?1? to individual bits. when ac- cessing these registers, writing a ?0? to a register that can only be set to a ?1? by the cpu will have no affect on that register bit. each figure and description of the special function registers will detail this operation. the usb control register (usbc) , shown in figure 1.52, is used to control the usb fcu. a usb reset signaling does not reset this register. after the usb is enabled (usbc7 set to ?1?), a minimum delay of 250 ns (three 12mhz clock periods) is needed before per- forming any other usb register read/write operations. the usb function address register (usba), shown in figure 1.53, maintains the 7-bit usb ad- dress assigned by the host. the usb fcu uses this register value to decode usb token packet ad- dresses. at reset, when the device is not yet configured, the value is 00 16 . fig. 1.52. usb control register (usbc) fig. 1.53. function address register (usba) reserved funad5 funad3 funad1 msb 7 lsb 0 address: 0050 16 access: r/w reset: 00 16 funad6 funad0 funad4 funad2 funad6:0 7-bit programmable function address (bit 6-0) bit 7 reserved (read/write ?0?) bit 0 reserved (read/write ?0?) usbc1 usb default state selection bit (bit 1) 0: in default state after power/reset 1: in default state after usb reset signaling received bit 2 reserved (read/write ?0?) usbc3 transceiver voltage converter high/low current mode select bit (bit 3) 0: high current mode 1: low current mode usbc4 usb transc eiver voltage converter bit (bit 4) 0: usb transceiver voltage converter disabled 1: usb transceiver vlotage converter enabled usbc5 usb clock enabled bit (bit 5) 0: 48 mhz clock to the usb block is disabled 1: 48 mhz clock to the usb block is enabled usbc6 usb sof port select bit (bit 6) 0: usb sof output is disabled p7 0 is used to gpio pin 1: usb sof output is enabled usbc7 usb enable bit (bit 7) 0: usb block is disabled, all usb internal registers are held at their default values 1: usb block is enabled usbc7 usbc5 usbc4 reserved usbc1 msb 7 lsb 0 address: 0013 16 access: r/w reset: 00 16 usbc6 usbc3 reserved
55 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer the usb power management register , shown in figure 1.54, is used for power management in the usb fcu. ? usb suspend detection flag (suspend) when the usb fcu does not detect any bus activ- ity on d+/d- for at least 3ms, it sets the suspend detection flag (suspend) and generates an inter- rupt. this bit is cleared when signaling (from the host) is detected on d+/d- [which sets the resume detection flag (resume) and generates an inter- rupt] or the remote wake-up bit (wakeup) is set and then cleared by the cpu. if the usb clock was disabled during the suspend state, the suspend bit is not cleared until after the usb clock is re-en- abled. ? usb resume detection flag (resume) when the usb fcu is in the suspend state and de- tects signaling on d+/d- (from the host), it sets the resume detection flag (resume) and generates an interrupt. the cpu writes a ?1? to inst14 (bit 6 of usb interrupt status register 2) to clear this flag. ? usb remote wake-up bit (wakeup) the cpu writes a ?1? to the wakeup bit for remote wake-up. while this bit is set, and the usb fcu is in suspend mode, it will generate resume signaling to the host. the cpu must keep this bit set for a minimum of 10ms and a maximum of 15ms before writing a ?0? to this bit. fig. 1.54. usb power management register (usbpm) suspend usb suspend detection flag (bit 0) (read only) 0: no usb suspend detected 1: idle state for greater than 3ms (usb suspend) detected resume usb resume detection flag (bit 1)(read only) 0: no usb resume signaling detected 1: usb resume signaling detected wakeup usb remote wake-up bit (bit 2) 0: end remote resume signaling 1: send remote resume signaling (only if suspend = ?1?) bit7:3 reserved (read/write ?0?) reserved reserved reserved wakeup resume msb 7 lsb 0 address: 0051 16 access: r/w reset: 00 16 reserved reserved suspend
56 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer the usb fcu is able to generate a usb function in- terrupt as discussed in section 1.21.2.1. the usb interrupt status registers (usbis1, usbis2) , shown in figure 1.55 and figure 1.56, are used to in- dicate the condition that caused a usb function interrupt to be generated. a ?1? indicates that the cor- responding condition caused a usb function interrupt. the usb interrupt status register can be cleared by writing back to the register the same value that was read. to ensure proper operation, the cpu should read both usb interrupt status registers, then write back the same values it read to these two registers for clearing the status bits. the cpu must write to usb interrupt status register 1 first and then to usb inter- rupt status register 2. the registers cannot be cleared by writing a ?0? to the bits that are a ?1?. fig. 1.55. usb interrupt status register 1 (usbis1) intst0 usb endpoint 0 interrupt status flag (bit 0) bit 1 reserved (read/write ?0?) intst2 usb endpoint 1 in interrupt status flag (bit 2) intst3 usb endpoint 1 out interrupt status flag (bit 3) intst4 usb endpoint 2 in interrupt status flag (bit 4) intst5 usb endpoint 2 out interrupt status flag (bit 5) intst6 usb endpoint 3 in interrupt status flag (bit 6) intst7 usb endpoint 3 out interrupt status flag (bit 7) 0: no interrupt request issued 1: interrupt request issued intst7 intst5 intst4 intst2 reserved msb 7 lsb 0 address: 0052 16 access: r/w reset: 00 16 intst6 intst3 intst0 fig. 1.56. usb interrupt status register 2 (usbis2) intst8 usb endpoint 4 in interrupt status flag (bit 0) intst9 usb endpoint 4 out interrupt status flag (bit 1) bit 3:2 reserved (read/write ?0?) intst12 usb overrun/underrun interrupt status flag (bit 4) intst13 usb reset interrupt status flag (bit 5) intst14 usb resume signaling interrupt status flag (bit 6) intst15 usb suspend signaling interrupt status flag (bit 7) 0: no interrupt request issued 1: interrupt request issued intst15 intst13 intst12 reserved intst9 msb 7 lsb 0 address: 0053 16 access: r/w reset: 00 16 intst14 r eserved intst8
57 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer the usb interrupt enable registers (usbie1, usbie2) shown in figure 1.57 and figure 1.58, are used to enable the corresponding interrupt status conditions that can generate a usb function interrupt. if the bit to a corresponding interrupt condition is ?0?, that condition will not generate a usb function inter- rupt. if the bit is a ?1?, that condition can generate a usb function interrupt. upon reset, all usb interrupt status conditions are enabled except the usb sus- pend signaling interrupt (bit 7 of usb interrupt enable register 2), which is disabled. the usb reset inter- rupt and usb resume signaling interrupt are always enabled. intst0 is set to a ?1? by the usb fcu if (in endpoint 0 in csr): ?a packet of data is successfully received ?a packet of data is successfully sent ?in0csr3 (data_end) bit is cleared (by usb fcu) ?in0csr4 (force_stall) bit is set (by the usb fcu) ?in0csr5 (setup_end) bit is set (by the usb fcu) fig. 1.57. usb interrupt enable register 1 (usbie1) fig. 1.58. usb interrupt enable register 2 (usbie2) inten7 inten5 inten4 inten2 reserved msb 7 lsb 0 address: 0054 16 access: r/w reset: ff 16 inten6 inten3 inten0 intst0 usb endpoint 0 interrupt status flag (bit 0) bit 1 reserved (read/write ?0?) intst2 usb endpoint 1 in interrupt enable bit (bit 2) intst3 usb endpoint 1 out interrupt enable bit (bit 3) intst4 usb endpoint 2 in interrupt enable bit (bit 4) intst5 usb endpoint 2 out interrupt enable bit (bit 5) intst6 usb endpoint 3 in interrupt enable bit (bit 6) intst7 usb endpoint 3 in interrupt enable bit (bit 7) 0: interrupt disabled 1: interrupt enabled intst2, intst4, intst6 or intst8 is set to a ?1? by usb fcu if (in endpoint x in csr): ?a packet of data is successfully sent ?inxcsr1 (under_run) bit is set (by usb fcu) intst3, intst5, intst7 or intst9 is set to a ?1? by usb fcu if (in endpoint xout csr): ?a packet of data is successfully received ?outxcsr1 (over_run) bit is set (by usb fcu) ?outxcsr4 (force_stall) bit is set (by usb fcu) intst12 is set to a ?1? by the usb fcu if an overrun or underrun condition occurs in any of the endpoints. intst13 is set to a ?1? by the usb fcu if usb reset signaling from the host is received. all usb internal registers other than this bit are reset to their default values when the usb reset is received. intst14 is set to a ?1? by the usb fcu when the usb fcu is in the suspend state and non-idle signal- ing on d+/d- is received. intst15 is set to a ?1? by the usb fcu when d+/d- are in the idle state for more than 3ms. inten8 usb endpoint 4 in interrupt enable bit (bit 0) inten9 usb endpoint 4 out interrupt enable bit (bit 1) bit 3:2 reserved (read/write ?0?) intst12 usb overrun/underrun interrupt enable bit (bit 4) bit 5 reserved (read/write ?1?) bit 6 reserved (read/write ?0?) inten15 usb suspend signaling interrupt enable bit (bit 7) 0: interrupt disabled 1: interrupt enabled inten15 reserved inten12 r eserved inten9 msb 7 lsb 0 address: 0055 16 access: r/w reset: 33 16 reserved reserved inten8
58 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer the usb frame number low register (usbsofl) , shown in figure 1.59, contains the lower 8 bits of the 11-bit frame number received from the host. the usb frame number high register (usbsofh) , shown in figure 1.60, contains the up- per 3 bits of the 11-bit frame number received from the host. the usb endpoint index register (usbindex) , shown in figure 1.61, identifies the endpoint pair. it serves as an index to endpoint-specific in csr, out csr, in maxp, out maxp and out wrt cnt reg- isters. this register also contains two global bits, iso_upd and auto_fl, which affect isochronous data trans- fers for endpoints 1-4. fig. 1.59. usb frame number low register (usbsofl) fig. 1.60. usb frame number high register (usbsofh) fig. 1.61. usb endpoint index register (usbindex) if iso_upd = ?0?, a data packet in an endpoint?s in fifo is always ?ready to transmit? upon receiving the next in_token from the host (with matched address and endpoint number). if iso_upd = ?1? and the iso bit of the corresponding endpoint?s in csr is set, then the internal ?ready to transmit? signal to the trans- mit control logic is delayed until the next sof. in this way the data loaded in frame n will be transmitted out in frame n+1. the iso_upd bit is a global bit for end- points 1 to 4, and works with isochronous pipes only. if auto_fl = ?1?, iso_upd = ?1?, and a particular in endpoint?s iso bit is set, then when the usb fcu de- tects an sof packet, if the corresponding in endpoint?s in_pkt_rdy = ?1?, the usb fcu auto- matically flushes the oldest packet from the in fifo. in this case, in_pkt_rdy = ?1? indicates that two data packet are in the in fifo. since, for iso trans- fer, double buffering is a requirement; maxp must set to be less than or equal to 1/2 of the fifo size. iso_upd r eserved reserved reserved epindx2 epindx1 epindx0 msb 7 lsb 0 auto_fl address: 0058 16 access: r/w reset: 00 16 epindx2:0 endpoint index: bit 2 bit 1 bit 0 0 0 0: function endpoint 0 0 0 1: function endpoint 1 0 1 0: function endpoint 2 0 1 1: function endpoint 3 1 0 0: function endpoint 4 others: undefined bits 3:5 reserved (read/write "0") auto_fl auto_flush bit (bit 6) 0: hardware auto fifo flush disabled 1: hardware auto fifo flush enabled iso_upd iso_update bit (bit 7) 0: iso_update disabled 1: iso_update enabled fn7 fn5 fn4 fn3 fn2 fn1 fn0 msb 7 lsb 0 fn6 address: 0056 16 access: r reset: 00 16 fn7:0 lower 8 bits of 11-bit frame number issued with a sof token reserved reserved reserved reserved fn10 fn9 fn8 msb 7 lsb 0 reserved address: 0057 access: r reset: 00 16 fn10:8 upper 3 bits of the 11-bit frame number issued with a sof token bits 7:3 reserved (read "0")
59 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer the usb endpoint 0 in csr control & status register , shown in figure 1.62, contains the control and status information of endpoint 0. in0csr0 (out_pkt_rdy): the usb fcu sets this bit to a ?1? upon receiving a valid setup/out token from the host. the cpu clears this bit after unloading the fifo, by way of writing a ?1? to in0csr6. the cpu should not clear the out_pkt_rdy bit before it finishes decoding the host request. if in0csr2 (send_stall) needs to be set (because the cpu decodes an invalid or unsupported request), the set- ting of in0csr6 = ?1? and in0csr2 = ?1? should be done in the same cpu write. in0csr1 (in_pkt_rdy): the cpu writes a ?1? to this bit after it finishes writing a packet of data to the endpoint 0 fifo. the usb fcu clears this bit after the packet has been successfully transmitted to the host, or the in0csr5 (setup_end) bit is set. in0csr2 (send_stall): the cpu writes a ?1? to this bit if it decodes an invalid or unsupported request from the host. if the out_pkt_rdy bit is a ?1? at the time the cpu wants to set the send_stall bit is to a ?1?, the cpu must also set serviced_out_pkt_rdy to a ?1? to clear the out_pkt_rdy. the usb fcu returns a stall hand- shake for all subsequent in/out transactions (during control transfer data or status stages) while this bit is set. the cpu writes a ?0? to this bit to clear it. in0csr3 (data_end): for control transfers, the cpu writes a ?1? to this bit after it writes (in data phase) or reads (out data phase) the last packet of data from/ to the fifo. this bit indicates to the usb fcu that the specific amount of data in the setup phase has been transferred. the usb fcu will advance to the status phase once this bit is set. when the status phase completes, the usb fcu clears this bit. when this bit is set to a ?1? and the host again requests or sends more data to the device, the usb fcu returns a stall handshake and terminates the current control transfer. in0csr4 (force_stall): the usb fcu sets this bit to a ?1? to report an error status if the one of the follow- ing occurs: ? host sends an in or out token in the absence of a setup stage ? host sends a bad data toggle in the status stage, i.e. data0 is used ? host sends a bad data toggle in the setup stage, i.e. data1 is used ? host requests more data than specified in the setup stage, i.e. in token comes after data_end bit is set ? host sends more data than specified in the setup stage, i.e. out token comes after data_end bit is set ? host sends larger data packet than maxp size of the corresponding endpoint. inocsr7 inocsr5 inocsr4 inocsr3 inocsr2 inocsr1 inocsr0 msb 7 lsb 0 inocsr6 address: 0059 16 access: r/w reset: 00 16 inocsr0 out_pkt_rdy flag (bit 0) (read only - write "0") 0: out packet is not ready 1: out packet is ready inocsr1 in_pkt_rdy bit (bit 1)(write "1" only or read) 0: in packet is not ready 1: in packet is ready inocsr2 send_stall bit (bit 2)(write "1" only or read) 0: no action 1: stall endpoint 0 by the cpu inocsr3 data_end bit (bit 3)(write "1" only or read) 0: no action 1: last packet of data transfered from/to the fifo inocsr4 force_stall flag (bit 4)(write "0" only or read) 0: no action 1: stall endpoint 0 by the usb fcu inocsr5 setup_end flag (bit 5) (read only - write "0") 0: no action 1: control transfer ended before the specific length of data is transferred during the data phase inocsr6 serviced_out_pkt_rdy bit (bit 6) (write only - read "0") 0: no change 1: clear the out_pkt_rdy bit (inocsr0) inocsr7 serviced_setup_end bit (bit 7)(write only - read "0") 0: no change 1: clear the setup_end bit (inocsr5) fig. 1.62. usb endpoint 0 in csr (in_csr)
60 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer all of the conditions stated on the preceeding page (except the bad data toggle in the setup state case) cause the device to send a stall handshake for the in/out token in question. in the bad data toggle in the setup stage case, the device sends ack for the setup stage and then sends stall for the next in/ out token. a stall handshake caused by the above conditions lasts for only one transaction and terminates the ongoing control transfer. any packet after the stall handshake will be seen as the begin- ning of a new control transfer. the cpu writes a ?0? to clear this force_stall status bit. in0csr5 (setup_end): the usb fcu sets this bit to a ?1? if a control transfer has ended before the spe- cific length of data is transferred during the data phase. the cpu clears this bit by way of writing a ?1? to in0csr7. once the cpu sees the setup_end bit set, it should stop accessing the fifo to service the previous setup transaction. if out_pkt_rdy is set at the same time that setup_end is set, it indi- cates that the previous setup transaction ended and a new setup token is in the fifo. in0csr6 and in0csr7: these bits are used to clear in0csr0 and in0csr5 respectively. writing a ?1? to these bits will clear the corresponding register bit. the usb endpoint x in csr , shown in figure 1.63, contains control and status information of the respec- tive in endpoint 1-4. the usb endpoint index register selects the specific endpoint. inxcsr0 (in_pkt_rdy) and inxcsr5 (tx_fifo_not_empty): these two bits are read together to determine in fifo status. a ?1? can be written to the inxcsr0 bit by the cpu to indicate a packet of data is written to the fifo (see chapter. for detail). inxcsr1 (under_run): this bit is used in iso mode only to indicate to the cpu that a fifo underrun has occurred. the usb fcu sets this bit to a ?1? at the beginning of an in token if no data packet is in the fifo. setting this bit will cause the inst12 bit of the interrupt status register 2 to set. the cpu writes a ?0? to clear this bit. inxcsr2 (send_stall): the cpu writes a ?1? to this bit when the endpoint is stalled (transmitter halt). the usb fcu returns a stall handshake while this bit is set. the cpu writes a ?0? to clear this bit. fig. 1.63. usb endpoint x in csr (in_csr) inxcsr7 inxcsr5 inxcsr4 inxcsr3 inxcsr2 inxcsr1 inxcsr0 msb 7 lsb 0 inxcsr6 address: 0059 16 access: r/w reset: 00 16 inxcsr0 in_pkt_rdy bit (bit 0)(write "1" only or read) 0: in packet is not ready 1: in packet is ready inxcsr1 under_run flag (bit 1)(write "0" only or read) 0: no fifo underrun 1: fifo underrun has occurred inxcsr2 send_stall bit (bit 2) 0: no action 1: stall in endpoint x by the cpu inxcsr3 iso/t oggle_init bit (bit 3) 0: select non-isochronous transfer (0->1->0) reset data toggle to data0 1: select isochronous transfer inxcsr4 intpt bit (bit 4) 0: select non-rate feedback interrupt transfer 1: select rate feedback interrupt transfer inxcsr5 tx_not_ept flag (bit 5) (read only - write "0") 0: transmit fifo is empty 1: transmit fifo is not empty inxcsr6 fl ush bit (bit 6) (write only - read "0") 0: no action 1: flush the fifo inxcsr7 aut o_set bit (bit 7) 0: auto_set disabled 1: auto_set enabled
61 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer inxcsr3 (iso/toggle_init): when the endpoint is used for isochronous data transfer, the cpu sets this bit to a ?1? for the entire duration of the isochronous transfer. with the iso bit set to a ?1?, the device uses data0 as the pid for all packets sent back to the host. when the endpoint is required to initialize the data toggle sequence bit (reset to data0 for the next data packet), the cpu sets this bit to a ?1? and then resets it to a ?0? to initialize the respective endpoint?s data toggle. as with any other method to initialize the data toggle, this set/reset of the toggle_init bit method as- sumes that there is no active in transaction to the respective endpoint on the bus at the time the initial- ization process is ongoing. set/reset of the toggle_init bit is performed only when an end- point experiences a configuration event. inxcsr4 (intpt): the cpu writes a ?1? to this bit to initialize this endpoint as a status change endpoint for in transactions. this bit is set only if the correspond- ing endpoint is to be used to communicate rate feedback information (see section 1.21.3.1 for de- tails). inxcsr5 (tx_fifo_not_empty): the usb fcu sets this bit to a ?1? when there is data in the in fifo. this bit in conjunction with in_pkt_rdy bit will pro- vide the transmit fifo status information (see section 1.21.3.1 for details). inxcsr6 (flush): the cpu writes a ?1? to this bit to flush the in fifo. if there is one packet in the in fifo, a flush will cause the in fifo to be empty. if there are two packets in the in fifo, a flush will cause the older packet to be flushed out from the in fifo. setting the inxcsr6 (flush) bit during trans- mission could produce unpredictable results. inxcsr7 (auto_set): if the cpu sets this bit to a ?1?, the in_pkt_rdy bit is set automatically by the usb fcu after the number of bytes of data equal to the maximum packet size (maxp) are written into the in fifo (see section 1.21.3.1 for details). all bits in usb endpoint 0 out csr (control & status register) , shown in figure 1.64, are reserved (all control and status information is in endpoint 0 in csr) fig. 1.64. usb endpoint 0 out csr (out_csr) bits 7:0 r eserved (read "0") reserved reserved reserved reserved reserved reserved reserved msb 7 lsb 0 reserved address: 005a 16 access: r reset: 00 16
62 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer the usb endpoint x out csr (control & status register) , shown in figure 1.65, contains control and status information of the respective out endpoint 1- 4. the usb endpoint index register selects the specific endpoint. outxcsr0 (out_pkt_rdy): the usb fcu sets this bit to a ?1? after it successfully receives a packet of data from the host. this bit is cleared by the cpu or by the usb fcu after a packet of data has been unloaded from the fifo (see section 1.21.3.2 for de- tails). outxcsr1 (over_run): this bit is used in iso mode only to indicate to the cpu that a fifo overrun has occurred. the usb fcu sets this bit to a ?1? at the beginning of an out token if the outxcsr0 (out_pkt_rdy) bit is not cleared. setting this bit will cause the inst12 bit of the interrupt status reg- ister 2 to set. the cpu writes a ?0? to clear this bit. outxcsr2 (send_stall): the cpu writes a ?1? to this bit when the endpoint is stalled (receiver halt). the usb fcu returns a stall handshake while this bit is set. the cpu writes a ?0? to clear this bit. outxcsr3 (iso/toggle_init): when the end- point is used for isochronous data transfer, the cpu sets this bit to a ?1? for the entire duration of the iso- chronous transfer. with the iso bit set to a ?1?, the device accepts either data0 or data1 for the pid sent by the host. when the endpoint is required to initialize the data toggle sequence bit (reset to data0 for the next data packet), the cpu sets this bit to a ?1? and then resets it to a ?0? to initialize the respective endpoint?s data toggle. as with any other method to initialize the data toggle, this set/reset of the toggle_init bit method as- sumes that there is no active out transaction to the respective endpoint on the bus at the time the initial- ization process is ongoing. set/reset of the toggle_init bit is performed only when an end- point experiences a configuration event. outxcsr4 (force_stall): the usb fcu sets this bit to a ?1? if the host sends out a larger data packet than the maxp size. the usb fcu returns a stall handshake while this bit is set. the cpu writes a ?0? to clear this bit. outxcsr5 (data_err): the usb fcu sets this bit to a ?1? to indicate the reception of a crc error or a bit stuffing error in an iso packet. the cpu writes a ?0? to clear this bit. outxcsr6 (flush): the cpu writes a ?1? to flush the out fifo. if there is one packet in the out fifo, a flush will cause the out fifo to be empty. if there are two packets in the out fifo, a flush will cause the older packet to be flushed out from the out fifo. setting the outxcsr6 (flush) bit dur- ing reception could produce unpredictable results. outxcsr7 (auto_clr): if the cpu sets this bit to a ?1?, the out_pkt_rdy bit is cleared automatically by the usb fcu after the number of bytes of data equal to the maximum packet size (maxp) is un- loaded from the out fifo (see section 1.21.3.2 for details). fig. 1.65. usb endpoint x out csr (out_csr) outxcsr7 outxcsr5 outxcsr4 outxcsr3 outxcsr2 outxcsr1 outxcsr0 msb 7 lsb 0 outxcsr6 address: 005a 16 access: r/w reset: 00 16 outxcsr0 out_pkt_rdy flag (bit 0) (write "0" onlyor read) 0: out packet is not ready 1: out packet is ready outxcsr1 over_run flag (bit 1) (write "0" only or read) 0: no fifo overrun 1: fifo overrun occurred outxcsr2 send_stall bit (bit 2) 0: no action 1: stall out endpoint x by the cpu outxcsr3 iso/toggle_init bit (bit 3) 0: select non-isochronous transfer (0->1->0) reset data toggle to data0) 1: select isochronous transfer outxcsr4 force_stall flag (bit 4) (write "0" only or read) 0: no action 1: stall endpoint x by the usb fcu outxcsr5 data_err flag (bit 5) (write "0" only or read) 0: no error 1: crc or bit stuffing error received in an iso packet outxcsr6 flush bit (bit 6) (write only - read "0") 0: no action 1: flush the fifo outxcsr7 auto_clr bit (bit 7) 1: auto_clr disabled 0: auto_clr enabled
63 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer the usb endpoint x in maxp , shown in figure 1.66, indicates the maximum packet size (maxp) of an endpoint x in packet. the default value for endpoint 0 and 2-4 is 8. the default value for endpoint 1 is 1. the cpu can change this value as negotiated with the host controller through the set_descriptor com- mand. the setting of this register also affects the configuration of single/dual packet operation. when maxp > 1/2 of the fifo size, single packet mode is set. when maxp <= 1/ 2 of the fifo size, dual packet mode is set. the usb endpoint x out maxp , shown in figure 1.67, indicates the maximum packet size (maxp) of an endpoint x out packet. the default value for end- point 0 and 2-4 is 8. the default value for endpoint 1 is 1. for endpoint 0, the in_maxp and out_maxp registers shadow each other. changing one register?s value effectively changes the other register?s value. the cpu can change this value as negotiated with the host controller through the set_descriptor com- mand. the setting of this register also affects the configuration of single/dual packet operation. when maxp > 1/2 of the fifo size, single packet mode is set. when maxp <= 1/2 of the fifo size, dual packet mode is set. the usb endpoint x out wrt cnt low and the usb endpoint x out wrt cnt high registers, shown in figure 1.68 and figure 1.69, contain the number of bytes in the endpoint x out fifo. the usb fcu sets the values in these two write count registers after having successfully received a packet of data from the host. the cpu reads these two reg- isters to determine the number of bytes to be read from the fifo. the cpu should read wrt cnt low first and then wrt cnt high. fig. 1.68. usb endpoint x out wrt cnt low register (wrt_cntl) fig. 1.69. usb endpoint x out wrt cnt high register (wrt_cnth) fig. 1.66. usb endpoint x in maxp register (in_maxp) fig. 1.67. usb endpoint x out maxp register (out_maxp) address: 005d 16 access: r reset: 00 16 w_cnt7:0 byte count. this register contains the lower 8 bits of the byte count register w_cnt7 w_cnt5 w_cnt4 w_cnt3 w_cnt2 w_cnt1 w_cnt0 msb 7 lsb 0 w_cnt6 omaxp7 omaxp5 omaxp4 omaxp3 omaxp2 omaxp1 omaxp0 msb 7 lsb 0 omaxp6 address: 005c 16 access: r/w omaxp7:0 maximum packet size (maxp) of endpoint x out packet maxp = n for endpoint 0,2,3,4 maxp = n * 8 for endpoint 1 n is the value written to this register. for endpoints that support a smaller fifo size, unused bits are not implemented(always write "0" to those bits) imaxp7 imaxp5 imaxp4 imaxp3 imaxp2 imaxp1 imaxp0 msb lsb imaxp6 address: 005b 16 imaxp7:0 maximum packet size (maxp) of endpoint x in packet maxp = n for endpoint 0,2,3,4 maxp = n * 8 for endpoint 1 n is the value written to this register. for endpoints that support a smaller w_cnt9:8 byte count. this register contains the upper 2 bits of the byte count register bits 7:2 r eserved (read "0") address: 005e 16 access: r reset: 00 16 reserved reserved reserved reserved reserved w_cnt9 w_cnt8 msb 7 lsb 0 reserved
64 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer the usb endpoint x fifo registers , shown in fig- ure 1.70 through figure 1.74, are the usb in (transmit) and out (receive) fifo data registers. the cpu writes data to these registers for the corre- sponding endpoint in fifo and reads data from these registers for the corresponding endpoint out fifo. fig. 1.70. usb endpoint 0 fifo register (usbfifo0) fig. 1.71. usb endpoint 1 fifo register (usbfifo1) fig. 1.72. usb endpoint 2 fifo register (usbfifo) fig. 1.73. usb endpoint 3 fifo register (usbfifo3) fig. 1.74. usb endpoint 4 fifo register (usbfifo4) address: 0060 16 access: r/w reset: n/a data_7:0 endpoint 0 in/out fifo register data_7 data_5 data_4 data_3 data_2 data_1 data_0 msb 7 lsb 0 data_6 address: 0061 16 access: r/w reset: n/a data_7:0 endpoint 1 in/out fifo register data_7 data_5 data_4 data_3 data_2 data_1 data_0 msb 7 lsb 0 data_6 address: 0063 16 access: r/w reset: n/a data_7:0 endpoint 3 in/out fifo register data_7 data_5 data_4 data_3 data_2 data_1 data_0 msb 7 lsb 0 data_6 address: 0064 16 access: r/w reset: n/a data_7:0 endpoint 4 in/out fifo register data_7 data_5 data_4 data_3 data_2 data_1 data_0 msb 7 lsb 0 data_6 address: 0062 16 access: r/w reset: n/a data_7:0 endpoint 2 in/out fifo register data_7 data_5 data_4 data_3 data_2 data_1 data_0 msb 7 lsb 0 data_6
65 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer data bus input data bus buffer 0 output data bus buffer 0 u 7 u 6 u 5 u 4 a 00 u 2 ibf 0 b 7 b 0 system bus obf 0 b 1 b 0 data bus buffer control register 0 obf 0 ibf 0 a 0 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 s 0 r w rd wr dbb 0 dbbs 0 input data bus buffer 1 output data bus buffer 1 u 7 u 6 u 5 u 4 a 01 u 2 ibf 1 b 7 b 0 obf 1 b 1 b 0 data bus buffer control register 1 obf 1 ibf 1 a 0 s 1 r w rd wr dbb 1 dbbs 1 fig. 1.75. bus interface circuit fig. 1.76. data bus buffer interrupt request circuit one-shot pulse generating circuit one-shot pulse generating circuit one-shot pulse generating circuit one-shot pulse generating circuit rising edge detection circuit rising edge detection circuit rising edge detection circuit rising edge detection circuit input buffer full interrupt request signal ibf output buffer empty interrupt request signal obe input buffer full flag 0 ibf0 input buffer full flag 1 ibf1 output buffer full flag 0 obf0 output buffer full flag 1 obf1 set interrupt request at this rising edge set interrupt request at this rising edge ibf0 ibf1 ibf obf1 obe (obe1) obf0 (obe0) 1.22 master cpu bus interface this device has a bus interface function with 2 i/o buff- ers that can be operated in slave mode by control signals from the master cpu (see figure 1.75). bus interface circuit). the bus interface can be connected directly to either a r/w type of cpu or a cpu with rd and wr separate signals. slave mode is selected with the bit 7 of the data buffer control register 0. the single data bus buffer mode and the double data bus buffer mode are selected with bit 7 of the data bus buffer control register 1. when selecting the double data bus buffer mode, port p72 becomes s 1 input. prior to enabling the mbi, port 6 must be placed in in- put mode by writing 00 16 to p6d (0015 16 ). when data is written to the mcu from the master cpu, an input buffer full interrupt request occurs. similarly, when data is read from the master cpu, an output buffer empty interrupt request occurs. when the bus interface is operating, dq 0 -dq 7 be- come a 3-state data bus that sends and receives data, command, and status to and from the master cpu. at the same time, w, r, s 0 , s 1 , and a 0 become host cpu control signal input pins. the two input buffer full interrupt requests and two out- put buffer full requests are multiplexed as shown in figure 1.76. the bus interface can be operated under normal mcu control or under on-chip dma control for fast data transfer. if a master cpu has a large amount of data to be transferred, use of the on-chip dma con- troller is highly recommended. the bus interface signal input level can be pro- grammed as cmos level (default) or as ttl level. bit7 of the port control register (ptc 7 ) is used for the input level selection.
66 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.22.1 data bus buffer status registers (dbbs0, dbbs1) the data bus buffer status register is an 8-bit register that indicates the data bus status, with bits 0, 1, and 3 being dedicated read-only bits. bits 2, 4, 5, 6, and 7 are user definable flags set by software, and can be read and write. when the a 0 pin is high, the master cpu can read the contents of this register. see fig- ures 1.77 to 1.80. output buffer full flag (obf 0 , obf 1 ) the obf 0 and the obf 1 flags are set high when data is written to the output data bus buffer by the slave cpu and is cleared to ?0? when data is read by the master cpu. input buffer full flag (ibf 0 , ibf 1 ) the ibf 0 and the ibf 1 flags are set high when data is written to the input data bus buffer by the master cpu and is cleared to ?0? when data is read by the slave cpu. a 0 flag (a0 0 , a0 1 ) the level of the a 0 pin is latched when data has been written from the host cpu to the input data bus buffer. 1.22.2 input data bus buffer registers (dbbin0, dbbin1) the data on the data bus is latched into dbbin0 or dbbin1 by a write request from the master cpu. the data in dbbin0 or dbbin1 can be read from the data bus buffer register in the sfr area. 1.22.3 output data bus buffer registers (dbbout0, dbbout1) data is set in dbbout0 or dbbout1 by writing to the data bus buffer register in the sfr area. when the a 0 pin is low, the data of this register is output by a read request from the host cpu. fig. 1.77. data bus buffer status register 0 (dbbs0) fig. 1.78. data bus buffer control register 0 (dbbc0) dbbc07 r eserved dbbc04 dbbc03 dbbco2 dbbc01 dbbc00 msb 7 lsb 0 address: 004a 16 access: r/w reset: 00 16 dbbc06 dbbc00 obf output selection bit (bit 0) 0: p5 2 pin is operated as gpio 1: p5 2 pin is operated as obf 0 output pin dbbc01 ibf output selection bit (bit 1) 0: p5 3 pin is operated as gpio 1: p5 3 pin is operated as ibf 0 output pin dbbc02 ibf 0 interrupt selection bit (bit 2) 0 : ibf 0 interrupt is generated by both write-data (a 0 = ?0?) and write- command (a 0 = ?1?) 1 : ibf 0 interrupt is generated by write-command (a 0 = ?1?) only dbbc03 output buffer 0 empty interrupt disable bit (bit 3) 0: enabled 1: disabled dbbc04 input buffer 0 full interrupt disable bit (bit 4) 0: enabled 1: disabled dbbc05 reserved (read/write ?0?) dbbc06 master cpu bus interface enable bit (bit 6) 0: p6 0 -p6 7 , p5 4 -p5 7 are gpio pins 1: p6 0 -p6 7 , p5 4 -p5 7 are bus interface signals dq0-dq7, s 0 , a 0 , r,w respectively dbbc07 bus interface type selection bit (bit 7) 0 : rd, wr separate type bus 1 : r/w type bus. dbbs07 dbbs05 dbbs04 dbbs03 dbbso2 dbbs01 dbbs00 msb 7 lsb 0 address: 0049 16 access: r/w reset: 00 16 dbbs06 dbbs00 output buffer full (obf 0 ) flag (bit 0) 0 : output buffer emopty. 1 : output buffer full. dbbs01 i nput buffer full (bf0) flag (bit 1) 0 : input buffer empty. 1 : input buffer full. dbbs02 user definable (u2) flag (bit 2) dbbs03 a 0 (a 00 ) flag (bit 3) indicates the a 0 status when ibf flag is set dbbs04 user definable (u4) flag (bit 4) dbbs05 user definable (u5) flag (bit 5) dbbs06 user definable (u6) flag (bit 6) dbbs07 user definable (u7) flag (bit 7)
67 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer fig. 1.79. data bus buffer status register 1 (dbbs1) fig. 1.80. data bus buffer control register 1 (dbbc1) dbbs17 dbbs15 dbbs14 dbbs13 dbbs12 dbbs11 dbbs10 msb 7 lsb 0 address: 004d 16 access: r/w reset: 00 16 dbbs16 dbbs10 output buffer full (obf 1 ) flag (bit 0) 0 : output buffer empty. 1 : output buffer full. dbbs11 i nput buffer full (bf0 1 ) flag (bit 1) 0 : input buffer empty. 1 : input buffer full. dbbs12 user definable (u2) flag (bit 3) dbbs13 a 0 (a 01 ) flag (bit 2) indicates the a 0 status when ibf flag is set dbbs14 user definable (u4) flag (bit 4) dbbs15 user definable (u5) flag (bit 5) dbbs16 user definable (u6) flag (bit 6) dbbs17 user definable (u7) flag (bit 7) dbbc17 r eserved dbbc14 dbbc13 dbbc12 dbbc11 dbbc10 msb 7 lsb 0 address: 004e 6 access: r/w reset: 00 16 reserved dbbc10 obf 1 output selection bit (bit 0) 0: p7 4 pin is operated as gpio 1: p7 4 pin is operated as pbf1 output pin if dbbc17 = ?1? dbbc11 ibf1 output selection bit (bit 1) 0: p7 3 pin is operated as gpio 1: p7 3 pin is operated as ibf 1 output pin if dbbc17= ?1? dbbc12 ibf1 interrupt selection bit (bit 2) 0 : ibf 1 interrupt is generated by both write-data (a 0 = ?0?) and write- command (a0 = ?1?) 1 : ibf 1 interrupt is generated by write-command (a 0 = ?1?)only dbbc13 output buffer 1 empty interrupt disable bit (bit 3) 0: enabled 1: disabled dbbc14 input buffer 0 full interrupt disable bit (bit 4) 0: enabled 1: disabled dbbc15 reserved (read/write ?0?) dbbc16 reserved (read/write ?0?) dbbc17 data bus buffer function selection bit (bit 7) 0 : single data bus buffer - p7 2 is used as bpio 1 : double data bus buffer - p7 2 is used as s 1 input
68 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.23 direct memory access controller this device contains a two-channel direct memory access controller (dmac). each channel performs fast data transfers between any two locations in the memory map initiated by specific peripheral events or software triggers. the main features of the dmac are as follows: ? two independent channels ? single-byte and burst transfer modes ? 16-bit source and destination address registers (for a 64k byte address space) ? 16-bit transfer count registers (for up to 64k bytes transferred before underflow) ? source/destination register automatic increment/decrement and no-change options ? source/destination/transfer count register reload on write or after transfer count register underflow options ? transfer requests from usb (9), mbi (4), external interrupts (4), uart1 (2), uart2 (2), sio (1), timerx (1), timery (1), timer1 (1), and software triggers ? closely coupled with usb and mbi for efficient data transfers ? interrupt generated for each channel when their respective transfer count register underflows ? fixed channel priority (channel 0 > channel 1) ? two cycles of required per byte transferred each channel of the dmac is made up of the following: ? 16-bit source and destination registers ? a 16-bit transfer count register ? two mode registers ? status flags contained in a status register shared by the two channels ? control and timing logic the 16-bit source and destination registers allow ac- cesses to any two locations in the 64k byte memory area. the 16-bit transfer count register decrements by one for each transfer performed and causes an interrupt and flag to be set when it underflows. the mode regis- ters control the configuration and operation of the dmac channel associated with the registers. a block diagram of the dmac is shown in figure 1.81. the sfr addresses for the two mode, source, destina- tion, and transfer count registers of a channel are the same for each channel. the accessible channel regis- ters are is determined by the value of the dmac channel index bit (dci) (bit 7 of the dmac index and status register (dmais). when this bit is a ?0?, channel 0 registers are accessible, and when this bit is a ?1?, channel 1 registers are accessible. the configuration of dmais and the mode registers are shown in figures 1.82, 1.83, 1.84, and 1.85. sample timing diagrams are shown in figures 1.86, 1.87, and 1.88, for a single-byte transfer initiated by a hardware source, a single-byte transfer initiated by the software trigger, and a burst transfer initiated by a hard- ware source, respectively. 0 15 mode reg 1 mode reg 2 temp reg ch 0 count latch data bus ch 0 timing generator address bus interrupts: uart1 rx & tx, sio, extint0, (d0cen; d0crr; (d0srce, d0srid, (d0drce. d0drid, dmac ch 0 (d0dwc) (d0dwc) (d0dwc) 0 15 int detect, i-flag ch 0 destination latch ch 0 destination reg 0 15 ch 0 source latch ch 0 source reg (d0tms) d0umie; d0swt; d0hrs3,2,1,0) (d0uf) interrupt dmac channel 0 dmac channel 1 index & data bus status reg signals: obe0, ibf0(data), ep1, ep2, ep3 out_pkt_rdy or int detect, i-flag interrupts: uart2 rx & tx, extint1, signals: obe1, ibf1(data), ep1, ep2, timer1, timerx, cntr0 ep4 out_pkt_rdy or (d0uf, d0sfi) (d1uf, d1sfi) ch 0 count reg timery, cntr1 ep1 out_fifo_not_empty ep out_fifo_not_empty d0rld) d0rld) (d0daue) int gen (dtsc) (drldd) (drldd) in_pkt_rdy, in_pkt_rdy, fig. 1.81. dmac block diagram
69 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer fig. 1.82. dmac index and status mode register (dmais) fig. 1.83. dmac channel x mode register 1 (dmaxm1) dxsrid dmac channel x source register increment/decrement select bit (bit 0) 0: increment after transfer 1: decrement after transfer dxsrce dmac channel x source register increment/decrement enable bit (bit 1) 0: increment/decrement disabled (no change after transfer) 1: increment/decrement enabled dxdrid dmac channel x destination resgister increment/decrement select bit (bit 2) 0: increment after transfer 1: decrement after transfer dxdrce dmac channel x destination register increment/decrement enable bit (bit 3) 0: increment/decrement disabled (no change after transfer) 1: increment/decrement enabled dxdwc dmac channel x data write control bit (bit 4) 0: write data in reload latches and registers 1: write data in reload latches only dxdaue dmac channel x disable after count register underflow enable bit (bit 5) 0: channel x not disabled after count register underflow 1: channel x disabled after count register underflow dxrld dmac channel x register reload bit (bit 6) 0: no action (bit is always read as ?0?) 1: setting to ?1? causes the source, destination, and transfer count registers of channel x to be reloaded dxtms dmac channel x transfer mode selection bit (bit 7) 0: single-byte transfer mode 1: burst transfer mode dxtms dxdaue dxdwc dxdrce dxdrid dxsrce dxsrid msb lsb address: 0040 16 access: r/w dxrld dci drldd dtsc disfi diuf dosfi douf msb 7 lsb 0 address: 003f 16 access: r/w reset: 00 16 reserved d0uf dmac channel 0 count register underflow flag (bit 0) 0 : channel 0 transfer count register underflow has not occurred 1 : channel 0 transfer count register underflow has occured d0sfi dmac channel 0 suspend (dur to interrupt service request) flag (bit 1) 0 : channel 0 transfer has not been suspended 1: channel 0 transfer has been suspended d1uf dmac channel 1 count register underflow flag (bit 2) 0 : channel 1 transfer count register underflow has not occurred 1 : channel 1 transfer count register underflow has occurred d1sfi dmac channel 1 suspend (due to interrupt service request ) flag (bit 3) 0 : channel 1 transfer has not been suspended 1; channel 1 transfer has been suspended dtsc dmac tr ansfer suspend control bit (bit 4) 0 : only burst transfers are suspended during interrupt servicing 1 : both burst and single-byte transfers are suspended during interrupt servicing drldd dmac re gister reload disable bit (bit 5) 0 : reload of source and destination registers of both channels enabled 1 : reload of source and destination registers of both channels disabled bit 6 reserved (read/write ?0?) dci channel index bit (bit 7) 0 : channel 0 mode,source, destination, and transfer count registers accessible 1 : channel 1 mode, source, destination, and transfer count registers accessible
70 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer fig. 1.84. dmac channel 0 mode register 2 (dma0m2) fig. 1.85. dmac channel 1 mode register 2 (dma1m2) d0hrs3,2,1,0 dmac channel 0 hardware transfer request source bits (bits 3,2,1,0) 0000: disable 0001: uart1 receive interrupt 0010: uart1 transmit interrupt 0011: timery interrupt 0100: external interrupt 0 0101: usb endpoint 1 in_pkt_rdy signal (falling edge active) 0110: usb endpoint 2 in_pkt_rdy signal (falling edge active) 0111: usb endpoint 3 in_pkt_rdy signal (falling edge active) 1000: usb endpoint 1 out_pkt_rdy signal (rising edge active) 1001: usb endpoint 1 out_fifo_not_empty signal (rising edge active) 1010: usb endpoint 2 out_pkt_rdy signal (rising edge active) 1011: usb endpoint 3 out_pkt_rdy signal (rising edge active) 1100: mbi obe 0 signal (rising edge active) 1101: mbi ibf 0 (data) signal (rising edge active) 1110: sio receive/transmit interrupt 1111: cntr1 interrupt doswt dmac channel 0 software transfer trigger (bit 4) 0: no action (bit is always read as ?0?) 1: writing ?1? requests a channel 0 transfer d0umie dmac channel 0 usb and mbi enable bit (bit 5) 0: disabled 1: enabled d0crr dmac channel 0 transfer initiation source capture register reset (bit 6) 0: no action (bit is always read as ?0?) 1: setting to ?1? causes reset of the channel 0 capture register d0cen dmac channel 0 enable bit (bit 7) 0: channel 0 disabled 1: channel 0 enabled d0cen d0umie d0swt d0hrs3 d0hrs2 d0hrs1 d0hrs0 msb lsb address: 0041 16 access: r/w d0crr d1hrs3,2,1,0 dmac channel 1 hardware transfer request source bits (bits 3,2,1,0) 0000: disable 0001: uart2 receive interrupt 0010: uart2 transmit interrupt 0011: timerx interrupt 0100: external interrupt 1 0101: usb endpoint 1 in_pkt_rdy signal (falling edge active) 0110: usb endpoint 2 in_pkt_rdy signal (falling edge active) 0111: usb endpoint 4 in_pkt_rdy signal (falling edge active) 1000: usb endpoint 1 out_pkt_rdy signal (rising edge active) 1001: usb endpoint 1 out_fifo_not_empty signal (rising edge active) 1010: usb endpoint 2 out_pkt_rdy signal (rising edge active) 1011: usb endpoint 4 out_pkt_rdy signal (rising edge active) 1100: mbi obe 1 signal (rising edge active) 1101: mbi ibf 1 (data) signal (rising edge active) 1110: timer interrupt 1111: cntr0 interrupt d1swt dmac channel 1 software transfer trigger (bit 4) 0: no action (bit is always read as ?0?) 1: writing ?1? requests a channel 0 transfer d1umie dmac channel 1 usb and mbi enable bit (bit 5) 0: disabled 1: enabled d1crr dmac channel 1 transfer initiation source capture register reset (bit 6) 0: no action (bit is always read as ?0?) 1: setting to ?1? causes reset of the channel 1 capture register d1cen dmac channel 1 enable bit (bit 7) 0: channel1 disabled 1: channel 1 enabled d1cen d1umie d1swt d1hrs3 d1hrs2 d1hrs1 d1hrs0 msb 7 lsb 0 address: 0041 16 access: r/w reset: 00 16 d1crr
71 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 3c 18 41 90 opcode2 dma data opcode3 dma dest. dma source 42,00 pc + 2 pc + 1 pc pc + 3 opcode5 address address pc + 4 ldm #$90, $41 single cycle dmac transfer inst. next inst. pc + 6 dma data out sync out rd wr address data dmac transfer signal (port3 3 ) transfer request source (active low) source sampling transfer request source sample latch reset transfer request opcode4 pc + 5 single cycle inst. single cycl inst. out sync out rd wr address data a5 adl1 data 85 dma data dma data adl2 adl2, 00 dma dest. dma source pc + 2 adl1, 00 pc + 1 pc pc + 3 opcode3 address address pc + 4 lda$zz sta $zz (first cycle) dmac transfer sta $zz (last 2 cycles) data dmac transfer signal (port3 3 ) transfer request source (active low) source sampling transfer request source sample latch reset transfe request next inst. a5 adl1 data 85 dma data1 dma data1 dma data2 dma dest. dma source pc + 2 adl1, 00 pc + 1 pc adl2 address1 address1 pc + 3 lda $zz sta $zz (first cycle) dmac transfer sta $zz (second cycle) dma data2 dma source address2 address2 dma dest. out sync out rd wr address data dmac transfer signal (port3 3 ) transfer request source (active low) source sampling transfer request source sample latch reset transfe request fig. 1.86. dmac transfer-hardware source initiated fig. 1.87. dmac transfer-software trigger initiated fig. 1.88. dmac transfer-burst transfer initiated
72 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.24 oscillator circuit an on-chip oscillator provides the system and periph- eral clocks as well as the usb clock necessary for operation. this oscillator circuit is comprised of ampli- fiers that provide the gain necessary for oscillation, oscillation control logic, a frequency synthesizer, and buffering of the clock signals. a clock control register (ccr) is shown in figure 1.89 and a flow diagram for the oscillator circuit is shown in figure 1.90. the following external clock inputs are supported: ? a quartz crystal oscillator of up to 24 mhz, connected to the x in and x out pins. ? a ceramic resonator or quartz crystal oscillator of 32.768 khz, connected to the xc in and xc out pins. ? an external clock signal of up to 5.00 mhz, connected to the xcin pin. the frequency synthesizer can be used to generate a 48mhz clock signal (f usb ) needed by the usb block and clock f syn , which can be chosen as the source for the system and peripheral clocks. both f usb and f syn are phase-locked frequency multiples of the fre- quency synthesizer input. the inputs to the frequency synthesizer can be either x in or xc in . the two-phase non-overlapping system clock (cpu and peripherals) is derived from the source to the clock circuit and is half the frequency of the source. (i.e. source = 24 mhz, system clock = 12 mhz) any one of four clock signals can be chosen as the source for the system and peripheral clocks; f(x in )/2, f(x in ), f(xc in ), or f syn . the selection is based on the values of bits cpma6, cpma7 and ccr7. the default source after reset is fxin/2. the default source for the system and peripheral clocks is f(x in )/2. if f(x in )= 24mhz, then the cpu will be running at = 6mhz (low frequency mode. for the cpu to run in high frequency mode, i.e., source of clock = f(x in ), write a ?1? to bit 7 of the clock control register. (if an external clock signal is input to x in or xc in , the inverting amplifiers can be disabled by means of the ccr6 and ccr7 bits, respectively, in or- der to reduce power consumption). bits 0-4 reserved (read/write ?0?) ccr5: xc out oscillation drive diable bit (bit 5). 0: xc out oscillation drive is enabled (when xc in oscillation is enabled). 1: xc out oscillation drive is disabled. ccr6: x out oscillation drive disable bit (bit 6). 0: xc out oscillation drive is enabled (when xc in oscillation is enabled). 1: xc out oscillation drive is disabled. ccr7: x in divider select bit (bit 7). 0: f(x in )/2 is used for the system clock source when cmpa 7:6=00. 1: f(x in ) is used for the system clock source when cmpa 7:6=10. ccr7 msb 7 lsb 0 address: 001f 16 access: r/w reset: 00 16 reserved reserved reserved reserved reserved ccr6 ccr5 fig. 1.89. clock control register (ccr)
73 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer note 1: stop mode stops the oscillators that are also the inputs to the frequency synthesizer. however, the frequency synthesizer is not disabled and so its output is unstable. so, always set the system clock to an external oscillator and disable the frequency synthesizer before entering stop mode. note 2: = f(x in )/4 can be interchanged with = f(x in )/2 by setting ccr7 to ?1?. the same flow chart applies to both cases. note 3: the input to the frequency synthesizer is independent of the system clock. it can be either x in or xc in depend ing on bit 3 of fsc. in the above flow, the input has been chosen to be the same as the system clock only for simplicity. the oscillator selected to be the input to the frequency synthesizer must be enable before the frequency synthesizer is enabled. note 4: the input clock for the frequency synthesizer must be set to xc in by setting fin (bit 3 of fsc) to a "1" before x in oscillation can be disabled. note: cpma values shown assume single-chip mode with stack in one page. x in clock stopped xc in clock on pll clock stopped =f(xc in )/2 cpma=bc, fsc=68 x in clock stopped xc in clock on pll clock on note 3 =f(xc in )/2 cpma7=bc, fsc=49 x in clock stopped xc in clock on pll clock on =f(pll)/2 cpma7=fc, fsc=49 x in clock on xc in clock on pll clock on =f(pll)/2 cpma=dc, fsc=41 x in clock on xc in clock on pll clock on note 3 =f(xc in )/2 cpma=9c, fsc=41 x in clock on xc in clock on pll clock stopped =f(xc in )/2 cpma=9c, fsc=60 x in clock on xc in clock on pll clock stopped =f(x in )/4 note 2 cpma=1c, fsc=60 x in clock on xc in clock on pll clock on note 3 =f(x in )/4 note 2 cpma=1c, fsc=41 x in clock on xc in clock on pll clock on =f(pll)/2 cpma=5c, fsc=41 x in clock on xc in clock stopped pll clock on =f(pll)/2 cpma=4c, fsc=41 stop note 1 wait stop note 1 wait stop note 1 wait stop note 1 wait wait wait wait wait reset fsc0 cpma6 10 cpma4 cpma7 cpma5 note 4 10 10 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 fsc0 fsc0 fsc0 cpma6 cpma6 cpma6 x in clock on xc in clock stopped pll clock stopped =f(x in )/4 note 2 cpma=0c, fsc=60 x in clock on xc in clock stopped pll clock on note 3 =f(x in )/4 note 2 cpma=0c fsc=41 fig. 1.90. clock flow diagram
74 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.24.1 frequency synthesizer circuit the frequency synthesizer circuit generates a 48mhz clock needed by the usb block and a clock f syn that are both a multiple of the external input reference clock f in . a block diagram of the circuit is shown in figure 1.91. the frequency synthesizer consists of a prescaler, fre- quency multiplier macro, a frequency divider macro, and four registers, namely fsm1, fsm2, fsc and fsd. two multiply registers (fsm1, fsm2) control the frequency multiply amount. clock f in is prescaled us- ing fsm2 to generate f pin . f pin is multiplied using fsm1 to generate an f vco clock which is then divided using fsd to produce the clock f syn . the f vco clock is optimized for 48 mhz operation and is buffered and sent out of the frequency synthesizer block as signal f usb . this signal is used by the usb block. the clock block diagram is shown in figure 1.92. clock f pin is a divided down version of clock f in , which can be either f(x in ) or f(xc in ). the default clock after re- set is fxin. the relationship between f pin and the clock input to the prescaler (f in ) is as follows: ?f pin = f in /2(n+1) where n is a decimal number between 0 and 254. (see figure 1.95). setting fsm2 to 255 disables the prescaler and f pin = f in . data bus fsm2 fsm1 fsc fsd 006e 006d 006c 006f frequency multiplier frequency divider 8 bit ls bit f in f vco f syn f usb prescaler 8 bit f pin the relationship between f pin , f vco , f syn , and f usb is as follows: ?f vco = f pin x 2(n+1) where n is the decimal equivalent of the value loaded in fsm1. (see figure 1.94). n must be chosen such that f vco equals 48 mhz. ?f syn = f vco / 2(m+1) where m is the decimal equiva- lent of the value loaded in fsd. (see figure 1.96). setting m=255 disables the divider and disables f syn . ?f usb is a buffered version of f vco , i.e., fsd has no ef- fect on f usb . setting usb control register bit 5 to ?0? disables f usb by tri-stating the buffer. the fsc0 bit in the fsc register (fsc) enables the frequency synthesizer block. when disabled (fsc0 = ?0?), f vco is held at either a high or low state. when the frequency synthesizer control bit is active (fsc0 = ?1?), a lock status (ls = ?1?) indicates that f syn and fvco are the correct frequency. the ls and fsco control bits in the fsc register are shown in figure 1.93. when using the frequency synthesizer, a low-pass fil- ter must be connected to the lpf pin. once the frequency synthesizer is enabled, a delay of 2-5ms is recommended before the output of the fre- quency synthesizer is used. this is done to allow the output to stabilize. it is also recommended that none of the registers be modified once the frequency syn- thesizer is enabled as it will cause the output to be temporarily (2-5ms) unstable. fig. 1.91. frequency synthesizer circuit
75 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer fse frequency synthesizer enable bit (bit 0) 0: disabled 1: enabled bit 2,1 r eserved (read/write ?0?) fin frequency synthesiszer input selector bit (bit 3) 0: x in 1: xc in bit 5,4 r eserved (read/write ?0?) bit 6 reserved (read/write ?1?) l s frequency synthesizer lock status bit (bit 7) (read only; write ?0?) 0: unlocked 1: locked ls msb 7 lsb 0 address: 006c 16 access: r/w reset: 60 16 fse reserved reserved fin reserved reserved reserved xoscstp d q t r pin1 d q t r r q s d q t d q t p2+ stp oscillator countdown timer 1->2 p2 peripheral p1 peripheral pin1 p2+ resetb r q s r q s d q t r q s d q t d q t s q r out p2 peripheral p1 peripheral p2 out p1 out p2+ pin2 stp slow memory wait p1+,p2+ rdy cpmb0 cpmb1 cpmb2 cpmb3 frequency synthesizer enable fsc0 cpma6 pin1,pin2 cpma7 f in f syn cpma5 oscstp delay stp padresetb i flag interrupt request x in x out f xin xc in xc out 1/2 cpma4 xoscstp xcoscstp xdoscstp xcdoscstp s r qb xcoscstp lpf f xcin lpf xcdoscstp xcod xdoscstp xod stp wit d q t r pin1 d q t r pin2 padresetb p1hatrstb p2latrstb p2latrstb p1hatrstb p2 p1 p2latrstb p1hatrstb lpf fin(fsc3) f ext 1/2 ccr7 2 (tw o phase) usb 48 mhz clock fig. 1.92. clock block diagram fig. 1.93. frequency synthesizer control register (fsc)
76 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer fig. 1.94. frequency synthesizer multiply control register (fsm1) fig. 1.95. frequency synthesizer multiply control register (fsm2) fig. 1.96. frequency synthesizer divided ratio register (fsd) address: 006d 16 access: r/w reset: ff 16 bit 0-7 frequency synthesizer multiply value, n, that is used to multiply the prescaler output frequency, f pin , up to 48.00 mhz bit 7 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 msb 7 lsb 0 bit 6 f vco = 2 x f pin x (n+1) f vco n 10 f pin n 16 fsm1 48.00 mhz 48.00 mhz 48.00 mhz 48.00 mhz 48.00 mhz 48.00 mhz 320.00 khz 0 4.00 mhz 6.00 mhz 12.00 mhz 24.00 mhz 74 11 5 3 1 4a 05 01 03 0b 2.00 mhz 00 address: 006e 16 access: r/w reset: ff 16 bit 0-7 frequency synthesizer prescaler divide value, n. the input clock, f in , is divided by this value to produce the intermediate frequency, f pin , which is then multiplied up to 48.00 mhz. a value of 255 (ff 16 ) turns the prescaler off (no division of f in ). bit 7 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 msb 7 lsb 0 bit 6 f pin = f in / (2 x (n+1)) f pin n 10 f in n 16 fsm2 24.00 mhz 1.00 mhz 2.00 mhz 3.00 mhz 6.00 mhz 12.00 mhz 24.00 mhz 0 24.00 mhz 24.00 mhz 24.00 mhz 24.00 mhz 255 11 5 3 1 ff 05 01 03 0b 24.00 mhz 00 address: 006f 16 access: r/w reset: ff 16 bit 0-7 frequency synthesizer divide value, m, by which the 48.00 mhz vco frequency is divided to produce the f syn system clock frequency. bit 7 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 msb 7 lsb 0 bit 6 f syn = f vco / (2 x (m+1)) f syn m 10 f vco m 16 fsd 24.00 mhz 8.00 mhz 4.00 khz 187.50 khz 93.75 khz 0.00 khz 48.00 mhz 255 48.00 mhz 48.00 mhz 48.00 mhz 48.00 mhz 0 2 5 127 128 00 05 80 7f 02 48.00 mhz ff
77 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.25 low power modes this device has two low-power dissipation modes: ?stop ?wait 1.25.1 stop mode use of the stop mode allows the mcu to be placed in a state where no internal excitation of the circuitry is taking place, thus resulting in extremely low power dissipation. the mcu enters the stop mode when the stp instruction is executed. the internal state of the mcu after execution of the stp instruction is as fol- lows: ?timer 1 and timer 2 are loaded with ff 16 and 01 16 respectively. ?all t123m mode register bits are reset to their default value except bit 4. ?the count source for timer 1 is set to /8 and the count source for timer 2 is set to timer 1 underflow. oscillation is restarted when a reset or an external in- terrupt is received. the interrupt control bit of the interrupt used to release the stop mode must be set to a "1" and the i flag set to a "0" prior to the execution of the stp instruction. to allow the oscillation source time to stabilize, the oscillation source is connected as the clock source for the wake-up timer (timer 1 and timer 2 cascaded). when timer 2 underflows, the mcu services the interrupt that caused the return from the stop state. afterwards, it services any other enabled interrupts that occurred, in the order of their respective priorities, and returns to its state prior to the execution of the stp instruction. the timing for the stp instruction is shown in figure 1.97. fig. 1.97. stp cycle timing diagram (stp) out sync out rd wr address data opcode invalid s,cpma2 pc + 1 pc x in intreq stpsig cpuosc (pc + 1)h sleep period timer countdown (oscillator stabilization) timer 2 underflow start of interrupt service routine ote: return from a stp instruction is caused by an interrupt, followed by the countdown and underflow of time 2
78 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.25.2 wait mode use of the wait mode allows the microcomputer to be placed in a state where excitation of the cpu is stopped, but the clocks to the peripherals continue to oscillate. this mode provides lower power dissipation during the idle periods and quick wake-up time. the microcomputer enters the wait mode when the wit instruction is executed. returning from wait mode is accomplished just as it is when returning from stop mode, with the exception that you need not provide time for the oscillator to sta- bilize, because the oscillation never stopped. additionally, any peripheral interrupt can be used to bring the microcomputer out of the wait mode. the timing for the wit instruction is shown in figure 1.98. out sync out rd wr address data opcode invalid s,cpma2 pc + 1 pc x in intreq stpsig (pc + 1) sleep period start of interrupt service routine note: return from a wit instruction is caused by a interrupt. fig. 1.98. wit cycle timing diagram (wit)
79 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 1.26 reset this device is reset if the reset pin is held low for a minimum of 2 s while the supply voltage is set be- tween 4.15 and 5.25v. when the reset pin returns high, the reset sequence commences (see figure 1.99). to allow the oscillation source the time to sta- bilize, a delay is generated by the countdown of timer 1 and timer 2 cascaded with ff 16 loaded in timer 1 and 01 16 loaded in timer 2. after the reset sequence completes, program execution begins at the address whose high-order byte is the contents of address fffa 16 and whose low-order byte is the contents of address fffb 16 . fig. 1.99. internal processing sequence after reset out sync out address data ? reset first timer countdown from 01ff 16 ? ? ? ? fffa fffb ? ? ? ? ? adh adl adl adh opcode
80 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 2.1 absolute maximum ratings table 2.1 absolute maximum ratings symbol parameter conditions limits unit v cc power supply -0.3 to 6.5 v av cc analog power supply -0.3 to v cc + 0.3 v v i input voltage p0, p1, p2, p3, p4, p5, p6, p7, p8 values are with respect to v ss . output transistors are in off state. -0.3 to v cc + 0.3 v v i input voltage reset, x in , xc in -0.3 to v cc + 0.3 v v i input voltage cnv ss -0.3 to 13 v v i input voltage usb d+, d- -0.5 to 3.8 v v o output voltage p0, p1, p2, p3, p4, p5, p6, p7, p8, x out , xc out, lpf -0.3 to v cc + 0.3 v v o output voltage usb d+, d- -0.5 to 3.8 v p d power dissipation (note) ta = 25 c 750 mw t opr operating temperature -20 to +85 c t stg storage temperature -40 to +125 c note: maximum power dissipation is based on heat dissipation characteristics not chip power consumption.
81 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 2.2 recommended operating conditions table 2.2. recommended operating conditions (vcc = 4.15 to 5.25v, vss = 0v, ta = -20 to 85 c unless otherwise noted) symbol parameter limits unit min. typ. max. v cc supply voltage 4.15 5 5.25 v av cc analog supply voltage 4.15 5 v cc v v ss supply voltage 0v av ss analog supply voltage 0v v ih h input voltage reset, x in , xc in , cnv ss 0.8v cc v cc v v ih h input voltage p0, p1, p2, p3, p4, p5, p6, p7, p8 0.8v cc v cc v v ih h input voltage p2 (when ptc6 = ? 0 ? ) 0.5v cc v cc v v ih h input voltage p5 7 -p5 4 , p6, p7 2 (when mbi inputs and ptc7 = ? 1 ? ) 2.0 v cc v v ih h input voltage usb d+, d- 2.0 3.8 v v il l input voltage reset, x in , xc in , cnv ss 0 0.2v cc v v il l input voltage p0, p1, p2, p3, p4, p5, p6, p7, p8 0 0.2v cc v v il l input voltage p2 (when ptc6 = ? 0 ? ) 0 0.16 v cc v v il l input voltage p5 7 -p5 4 , p6, p7 2 (when mbi inputs and ptc7 = ? 1 ? ) 0 0.8 v v il l input voltage usb d+, d- 0 0.8 v i ol (peak) l peak output current note 1 p0, p1, p2, p3, p4, p5, p6, p7, p8 10 ma i ol (avg) l average output current note 2 p0, p1, p2, p3, p4, p5, p6, p7, p8 5ma i oh (peak) h peak output current note 1 p0, p1, p2, p3, p4, p5, p6, p7, p8 -10 ma i oh (avg) h average output current note 2 p0, p1, p2, p3, p4, p5, p6, p7, p8 -5 ma ? ol (peak) l total peak output current note 3 p0, p1, p2, p3, p4, p5, p6, p7, p8 80 ma i ol (avg) l total average output current note 4 p0, p1, p2, p3, p4, p5, p6, p7, p8 40 ma i oh (peak) h total peak output current note 3 p0, p1, p2, p3, p4, p5, p6, p7, p8 -80 ma i ol (avg) h total average output current note 4 p0, p1, p2, p3, p4, p5, p6, p7, p8 -40 ma f(cntr0) timerx - input frequency note 5 5 mhz f(cntr1) timery - input frequency note 5 5 mhz f(x in ) clock frequency note 5 24 mhz f(xc in ) clock frequency note 5,6 32.768 50/5.0 khz/mhz 4 ,7 note 1. the peak output current is the peak current flowing through any pin of the listed ports. note 2. the average output current is an average current value measured over 100 ms. note 3. the total peak output current is the peak current flowing throught all pins of the listed ports. note 4. the total average output current is an average current value measured over 100 ms. note 5. the oscillation frequency has a 50% cycle. note 6. the maximum oscillation frequency of 50 khz is for a crystal oscillator connected between xcin and xcout. an external signal having a maximum frequency of 5 mhz can be input to xcin. note 7. when using frequency synthesizer circuit, minimum limit is 4 mhz. and when using usb, put internal clock f( )to more than 6 mhz.
82 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 2.3 electrical characteristics table 2.3. electrical characteristics (vcc = 4.15 to 5.25v, vss = 0v, ta = -20 to 85 c unless otherwise noted) symbol parameters test conditions limits unit min typ. max v oh h output voltage p0, p1, p2, p3, p4, p5, p6, p7, p8 ioh = -10ma v cc - 2.0 v v oh h output voltage usb d+, d- usb d+, usb d- pins pull down to vss by 15 k ? 5 % and usb d+ pin pull up to extcap pin by 1.5 k ? v ol l output voltage p0, p1, p2, p3, p4, p5, p6, p7, p8 iol = 10ma 2.0 v v ol l output voltage usb d+, d- usb d+, usb d- pins pull down to vss by 15 k ? 5 % and usb d+ pin pull up to extcap pin by 1.5 k ? v t + ~v t - hysteresis cntr0, cntr1, int0, int1, rdy, hold, p2 0.5 v urxd1, urxd2 (sclk), cts2 (srxd), srd y, cts1 0.5 v reset 0.5 v i ih h input current p0, p1, p2, p3, p4, p5, p6, p7, p8 v i = v cc 5 a reset, usb d+, usb d-, cnv ss 5 a x in 920 a xc in 5 a i il l input current p0, p1, p3, p4, p5, p6, p7, p8 v i = v ss -5 a p2 v i = v ss (pullups off) -5 a v cc = 5v, v i = v ss (pullups on) -30 -75 -140 a reset, usb d+, usb d- v i = v ss -5 a cnv ss -20 x in -9 -20 a xc in -5 a v ram ram retention voltage clocks stopped 2.0 v i cc supply current (output transistors are isolated) normal mode f(x in ) = 24mhz, = 12mhz, usb operating, frequency synthesizer on, note 1 wait mode f(x in ) = 24mhz, = 12mhz, usb suspended, frequency synthesizer on, usb clock disabled note 2 7.5 10 ma f(xc in ) = 32khz, = 16khz, usb disabled, frequency synthesizer off, transceiver voltage converter off note 3 610 a transceiver voltage converter on with usbc3 = ? 1 ? (low current mode) 200 250 a stop mode t a = 25 c , transceiver voltage converter off 0.1 1 a t a = 85 c , transceiver voltage converter off 10 a 2.8 3.6 0.3 5.25 70 90 ma 5% 5% v v note 1: icc test conditions note 2: icc test conditions note 3: icc test conditions single chip mode (run state) single chip mode (wait state) single chip mode (wait state) square wave clock input on x in (x out drive disabled) square wave clock input on x in (x out drive disabled) x in /x out oscillation disabled i/o pins isolated i/o pins isolated square wave clock input on xc in (xc out drive disabled) frequency synthesizer running frequency synthesizer running i/o pins isolated usb operating with transceiver voltage converter enabled usb in suspend state with usb clock dis abled frequency synthesizer disabled cpu and dmac running transceiver voltage converter enabled usb and usb clock disabled timers and scsg running timers and scsg running transceiver voltage converter disabled bothuarts transmitting cpu and dmac not running timers and scsg running mbi and sio disabled both uarts, sio, and mbi disabled cpu and dmac not running both uarts, sio, and mbi disabled
83 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 2.4 timing requirements and switching characterisctics table 2.4 timing requirements and switching characterisctics (vcc = 4.15 to 5.25v, vss = 0v, ta = -20 to 85c unless otherwise noted) limits unit symbol parameter min typ. max inputs tw(reset) reset input ? low ? pulse width 2 _s tc(x in ) clock input cycle time 41.66 ns twh(x in ) clock input ? high ? pulse width 0.4*tc(x in )ns twl(x in ) clock input ? low ? pulse width 0.4*tc(x in )ns tc(xc in ) clock input cycle time 200 ns twh(xc in ) clock input ? high ? pulse width 0.4*tc(xc in )ns twl(xc in ) clock input ? low ? pulse width 0.4*tc(xc in )ns interrupts tc(int) int0, int1 input cycle time 200 ns twh(int) int0, int1 input ? high ? pulse width 90 ns twl(int) int0, int1 input ? low ? pulse width 90 ns tc(cntri) cntr0, cntr1 input cycle time 200 ns twh(cntri) cntr0, cntr1 input ? high ? pulse width 80 ns twl(cntri) cntr0, cntr1 input ? low ? pulse width 80 ns timers td( -tout) timer tout delay time (note) 15 ns td( -cntr0) timer cntr0 delay time (pulse output mode) (note) 15 ns tc(cntre0) timer cntr0 input cycle time (event counter mode) 200 ns twh(cntre0) timer cntr0 input ? high ? pulse width (event counter mode) 0.4*tc(cntre0) ns twl(cntre0) timer cntr0 input ? low ? pulse width (event counter mode) 0.4*tc(cntre0) ns td( -cntr1) timer cntr1 delay time (pulse output mode) (note) 15 ns tc(cntre1) timer cntr1 input cycle time (event counter mode) 200 ns twh(cntre1) timer cntr1 input ? high ? pulse width (event counter mode) 0.4*tc(cntre1) ns twl(cntre1) timer cntr1 input ? low ? pulse width (event counter mode) 0.4*tc(cntre1) ns sio tc(sclke) sio external clock input cycle time 400 ns twh(sclke) sio external clock input ? high ? pulse width 190 ns twl(sclke) sio external clock input ? low ? pulse width 180 ns tsu(srxd-sclke) sio receive setup time (external clock) 15 ns th(sclke-srxd) sio receive hold time (external clock) 10 ns td(sclke-stxd) sio transmit delay time (external clock) 25 ns tv(sclke-srdy) sio srdy valid time (external clock) 26 ns tc(sclki) sio internal clock output cycle time 166.66 ns twh(sclki) sio internal clock output ? high ? pulse width 0.5*tc(sclki)-5 ns twl(sclki) sio internal clock output ? low ? pulse width 0.5*tc(sclki)-5 ns tsu(srxd-sclki) sio receive setup time (internal clock) 20 ns th(sclki-srxd) sio receive hold time (internal clock) 5 ns td(sclki-stxd) sio transmit delay time (internal clock) 5 ns _____ _____
84 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer table 2.4 timing requirements and switching characterisctics (continued) (vcc = 4.15 to 5.25v, vss = 0v, ta = -20 to 85c unless otherwise noted) limits unit symbol mbi (separate r and w type mode) parameter min typ. max tsu(s-r) s 0 , s 1 setup time for read 0 ns tsu(s-w) s 0 , s 1 setup time for write 0 ns th(r-s) s 0 , s 1 hold time for read 0 ns th(w-s) s 0 , s 1 hold time for write 0 ns tsu(a-r) a 0 setup time for read 10 ns tsu(a-w) a 0 setup time for write 10 ns th(r-a) a 0 hold time for read 0 ns th(w-a) a 0 hold time for write 0 ns tw(r) read pulse width 50 ns tw(w) write pulse width 50 ns tsu(d-w) data input setup time before write 25 ns th(w-d) data input hold time after write 0 ns ta(r-d) data output enable time after read 40 ns tv(r-d) data output disable time after read 10 ns tv(r-obf) obf output transmission time after read 40 ns td(w-ibf) ibf output transmission time after write 40 ns mbi (r/w type mode) tsu(s-e) s 0 , s 1 setup time 0 ns th(e-s) s 0 , s 1 hold time 0 ns tsu(a-e) a 0 setup time 10 ns th(e-a) a 0 hold time 0 ns tsu(r/w-e) r/w setup time 10 ns th(e-r/w) r/w hold time 10 ns tw(e) enable pulse width 50 ns tw(e-e) enable pulse interval 50 ns tsu(d-e) data input setup time before write 25 ns th(e-d) data input hold time after write 0 ns ta(e-d) data output enable time after read 40 ns tv(e-d) data output disable time after read 10 ns tv(e-obf) obf output transmission time after e inactive 40 ns td(e-ibf) ibf output transmission time after e inactive 40 ns _ _ _ _ __ _ _ _ _ __ __ __ _ _ _ _ _ _ _ _ _
85 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer tw(reset) 0.2vcc 0.8vcc reset x in 0.2vcc 0.8vcc twh(x in ) twl(x in ) tc(x in ) xc in 0.2vcc 0.8vcc twh(xc in ) twl(xc in ) tc(xc in ) interrupts cntr0, cntr1 0.2vcc 0.8vcc twh(int),twh(cntri) twl(int),twl(cntri) int0, int1 , tc(int), tc(cntri) timers tout 0.5vcc td( -tout) cntr0, cntr1 td( -cntr0,1) inputs 0.5vcc 0.5vcc cntr0, cntr1 0.2vcc 0.8vcc twh(cntre0,1) twl(cntre0,1) tc(cntre0,1) _____ _____ _______ fig. 2.1. reset, clock, interrupts and timers timing diagram
86 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer s0, s1 t su(s-w) t h(w-s) 0.2vcc (0.8v) read write a 0 s0, s1 r dq 0 -dq 7 obf ibf dq 0 -dq 7 a 0 t su(a-r) t h(r-a) t su(s-r) t h(r-s) t w(r) t a(r-d) t v(r-d) t v(r-obf) t su(a-w) t h(w-a) t su(d-w) t h(w-d) t d(w-ibf) 0.8vcc (2.0v) 0.2vcc (0.8v) 0.2vcc 0.2vcc (0.8v) 0.8vcc (2.0v) 0.2vcc (0.8v) 0.8vcc 0.2vcc 0.8vcc 0.2vcc 0.8vcc (2.0v) 0.2vcc (0.8v) w t w(w) 0.8vcc (2.0v) 0.2vcc (0.8v) 0.2vcc note: ttl input levels in parenthesis (ttl levels selected when ptc7 = ? 1 ? ) 0.8vcc (2.0v) 0.2vcc (0.8v) __ __ __ a 0 read obf, ibf dq 0 -dq 7 t su(a-e) t h(e-a) t su(s-e) t h(e-s) t a(e-d) t v(e-d) e t w(e-e) t w(e) s0, s1 write dq 0 -dq 7 t h(e-d) t v(e-obf) t d(e-ibf) r/ w t su(e-d) 0.8vcc (2.0v) 0.2vcc (0.8v) 0.2vcc (0.8v) 0.2vcc (0.8v) 0.8vcc (2.0v) 0.2vcc (0.8v) 0.8vcc 0.2vcc 0.8vcc (2.0v) 0.2vcc (0.8v) 0.2vcc t h(e-rw) __ fig. 2.2. mbi timing diagram (separate r and w type mode) fig. 2.3. mbi timing diagram (r/w type mode)
87 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer table 2.5. memory expansion mode and microprocessor mode timing (vcc = 4.15 to 5.25v, vss = 0v, ta = -20 to 85c unless otherwise noted) note : measurement conditions: iohl = 5ma, c l = 50pf symbol parameter limits unit min. typ. max. tc( ) clock cycle time 83.33 ns twh( ) clock ? h ? pulse width 0.5*tc( )-5 ns twl( ) clock ? l ? pulse width 0.5*tc( )-5 ns td( -ah) address bus ab15-ab8 delay time with respect to 31 ns tv( -ah) address bus ab15-ab8 valid time with respect to 5ns td( -al) address bus ab7-ab0 delay time with respect to 33 ns tv( -al) address bus ab7-ab0 valid time with respect to 5ns td( -wr) wr delay time 6ns tv( -wr) wr v alid time 3 ns td( -rd) rd delay time 6ns tv( -rd) rd valid time 3 ns td( -sync) sync out delay time 6ns tv( -sync) sync out valid time 4ns td( -dma) dma out delay time 25 ns tv( -dma) dma out valid time 5ns tsu(rdy- ) rdy setup time with respect to 21 ns th( -rdy) rdy hold time with respect to 0ns tsu(hold- ) hold setup time 21 ns th( -hold) hold hold time 0ns td( -hldal) hldal delay time 25 ns tv( -hldah) hldah delay time 25 ns tsu(db- ) data bus setup time with respect to 7ns th( -db) data bus hold time with respect to 0ns td( -db) data bus delay time with respect to 22 ns tv( -db) data bus valid time with respect to (note) 13 ns twl(wr) wr pulse width 0.5*tc( )-5 ns twl(rd) rd pulse width 0.5*tc( )-5 ns td(ah-wr) wr delay time after stable address ab15-ab8 0.5*tc( )-28 ns td(al-wr) wr delay time after stable address ab7-ab0 0.5*tc( )-30 ns tv(wr-ah) address bus ab15-ab8 valid time with respect to wr 0ns tv(wr-al) address bus ab7-ab0 valid time with respect to wr 0 ns td(ah-rd) rd delay time after stable address ab15-ab8 0.5*tc( )-28 ns td(al-rd) rd delay time after stable address ab7-ab0 0.5*tc( )-30 ns tv(rd-ah) address bus ab15-ab8 v alid time with respect to rd 0ns tv(rd-al) address bus ab7-ab0 valid time with respect to rd 0ns tsu(rdy-wr) rdy setup time with respect to wr 27 ns th(wr-rdy) rdy hold time with respect to wr 0 ns tsu(rdy-rd) rdy setup time with respect to rd 27 ns th(rd-rdy) rdy hold time with respect to rd 0 ns tsu(db-rd) data bus setup time with respect to rd 13 ns th(rd-db) data bus hold time with respect to rd 0ns td(wr-db) data bus delay time with respect to wr 20 ns tv(wr-db) data bus valid time with respect to wr note 10 ns tr(d+), tr(d-) usb output rise time, cl=50 pf 4 20 ns tf (d+), tf(d-) usb output fall time, cl=50 pf 4 20 ns
88 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer fig. 2.4. microprocessor and memory expansion mode timing diagram 1 ab15-ab8 ab7-ab0 sync out rd, wr rdy db0-db7 (cpu read phase) db0-db7 (cpu write phase) t c( ) 0.5vcc td( - ah) 0.5vcc twh( ) td( - al ) th( - rdy) tsu(rdy - ) td( - db) tv( - db) tsu(db - ) td( - rd ) 0.5vcc 0.8vcc 0.2vcc 0.8vcc 0.2vcc 0.5vcc th( - db) tv( - rd) tv( - al) tv( - ah) twl( ) 0.5vcc 0.5vcc dma out td( - sync ) 0.5vcc td( - dma ) 0.5vcc tv( - dma) hold th( - hold) tsu(hold - ) 0.8vcc 0.2vcc hld a td( - hldal) tv( - sync) (n cycles of ) hold th( - hold) tsu(hold - ) 0.8vcc 0.2vcc hld a td( - hldah) (enter state) (exit state) 0.5vcc 0.5vcc td( - wr ) tv( - wr) usb d+ tr( d- ) 0.9voh usb d- tr( d+ ) tf( d+ ) 0.1voh tf( d- ) _______ _______ _______ _______ _______ _______
89 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer ab15-ab8 ab7-ab0 rd , wr rdy db0-db7 (cpu read phase) db0-db7 (cpu write phase) 0.5vcc th(rd - rdy) tsu(rdy - rd) td(wr - db) tv(wr - db) tsu(db - rd) 0.5vcc 0.8vcc 0.2vcc 0.8vcc 0.2vcc 0.5vcc th(rd - db) twl(rd), twl(wr) tv(rd - ah) 0.5vcc tv(wr - ah) td(ah - rd) td(ah - wr) tv(rd - al) tv(wr - al) td(al - rd) td(al - wr) th(wr - rdy) tsu(rdy wr) ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ tc(sclke,i) 0.2vcc 0.8vcc sio 0.8vcc 0.2vcc tsu(srxd-sclke,i) th(sclke,i-srxd) td(sclke,i-stxd) tv(sclke-srdy) 0.8vcc sclk srxd stxd srdy twh(sclke,i) twl(sclke,i) 0.5vcc __ fig. 2.5. microprocessor and memory expansion mode timing diagram 2 fig. 2.6. sio timing diagram fig. 2.7. output switching characteristics measurements circuits measurement output pin 100pf cmos output measurement output pin 100pf n-channel open-drain output 1k ?
90 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer data required for mask orders the following are necessary when ordering a mask rom production: 1. mask rom order confirmation form 2. mark specification form 3. data to be written to rom, in eprom form three identical copies) or in floppy disk form. rom programming method the built-in prom of the blank one-time prom ver- sion and built-in eprom version can be read or programmed with a general-purpose prom program- mer using a special programming adapter. (see table 2.6). the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to ensure proper operation after programming, the procedure shown in figure 2.8 is recommended to verify programming. programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer functional check in target device the screening temperature is far higher than the storage temperature. never expose to 150 c exceeding 100 hours. caution : name of programming adapter pca7440fp pca7440fs table 2.6. programming adapter package 80p6n-a 80d0 fig. 2.8. programming and testing of one-time prom version
91 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer 740 family mask rom confirmation form single-chip microcomputer m37640m8-xxxfp mitsubishi electric gzz-sh57-30b<9xa0> * 1. mark specification mark specification must be submitted using the correct form for the package being ordered. fill out the appropriate mark specification form 80p6n and attach it to the mask rom confirmation form. * 2. usage conditions please answer the following questions about usade for use in our product inspection. (1) how will you use the x in -x out oscillator? at what frequency? f(x in ) = (2) which function will you use the pins p5 0 /x cin and p5 1 /xc out as p5 0 and p5 1 , or xc in and xc out ? quartz crystal other ( ) ports p5 0 and p5 1 function external clock input xc in and xc out function (external resonator) mhz * 3. comments we recommend the use of the following pseudo-command to set the start address of the assembler source program because ascii codes of the product name are written to addresses 0000 16 to 0008 16 of eprom. note : if the name of the product written to the eproms does not match the name of the mask confirmation form, the rom will not be processed. file code (hexadecimal notation) mask file name .msk (equal or less than eight characters) ordering by floppy disk we will produce masks based on the mask file generating utility. we shall assume the responsibility for errors only if the mask rom data on the products differs from this mask file. therefore, extreme care must be taken to verify the accuracy of the mask file submitted. the floppy disk must be 3.5-inch 2hd type and dos/v format. only one mask file per floppy disk should be submitted. mask rom number 27512 *= $0000 eprom type the pseudo-command .byte ?m37640m8-?
92 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer gzz-sh57-30b<9xa0> 740 family mask rom confirmation form single-chip microcomputer m37640m8-xxxfp mitsubishi electric note : please fill in all items marked *. *1 confirmation three eproms are required for each pattern if this order is performed by eproms. one floppy disk is required for each pattern if this order is performed by a floppy disk. checksum code for entire eprom (hexadecimal notation) in the address space of the microcomputer, the internal rom area is from ad- dress 8080 16 to fffb 16 . the reset vector is stored in addresses fffa 16 and fffb 16 . (1) set the data in the unused area (the shaded area of the diagram) to ?ff 16 ?. (2) the ascii codes of the product name ?m37640m8-? must be entered in addresses 0000 16 to 0008 16 . and set the data ?ff 16 ? in addresses 0009 16 to 000f 16 . the ascii codes and addresses are listed to the right in hexadecimal notation. eprom type (indicate the type used) ordering by eproms if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. 27512 eprom address 0000 16 000f 16 0010 16 807f 16 8080 16 fffb 16 fffc 16 ffff 16 product name ascii code : ?m37640m8-? data rom 32k-132 bytes address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 ?m? = 4d 16 ?3? = 33 16 ?7? = 37 16 ?6? = 36 16 ?4? = 34 16 ?0? = 30 16 ?m? = 4d 16 ?8? = 38 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 ?-? = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 receipt mask rom number date: section head signature supervisor signature company name customer issuance signature date issued submitted by tel () date: supervisor *
93 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer customer?s parts number note: the fonts and size of characters are standard mitsubishi type. mitsubishi ic catalog name notes 1: the mark field should be written right aligned. 2: the fonts and size of characters are standard mitsubishi type. 3: customer?s parts number can be up to 14 alphanu- meric characters for capital letters, hyphens, commas, periods and so on. 4: if the mitsubishi logo is not required, check the box below. mitsubishi ic catalog name please choose one of the marking types below (a, b, c), and enter the mitsubishi ic catalog name and the special mark (if neede d). notes 1: if special mark is to be printed, indicate the desired lay- out of the mark in figure c. the layout will be duplicated technically as close as possible. mitsubishi product num- ber (6-digit, or 7-digit) and mask rom number (3-digit) are always marked for sorting the products. 2: if special character fonts (e,g., customer?s trade mark logo) must be used in special mark, check the box below. for the new special character fonts, a clean font original (ideally logo drawing) must be submitted. special character fonts required mitsubishi ic catalog name 80p6n (80-pin qfp) mark specification form a. standard mitsubishi mark b. customer?s parts number + mitsubishi ic catalog name c. special mark required mitsubishi logo is not required 64 65 41 1 40 80 24 25 mitsubishi product number (6-digit, or 7-digit) 64 65 41 1 40 80 24 25 64 65 41 1 40 80 24 25
94 ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer qfp80-p-1420-0.80 1.58 weight(g) ? jedec code eiaj package code lead material alloy 42 80p6n-a plastic 80pin 14 ? 20mm body qfp ? 0.1 ? ?? 0.2 ? ? ?? ? ? ? ? ? symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.5 ? ? i 2 1.3 ? ? m d 14.6 ? ? m e 20.6 10 0 0.1 1.4 0.8 0.6 0.4 23.1 22.8 22.5 17.1 16.8 16.5 0.8 20.2 20.0 19.8 14.2 14.0 13.8 0.2 0.15 0.13 0.45 0.35 0.3 2.8 0 3.05 e e e e c h e 1 80 65 40 64 41 25 24 h d d m d m e a f a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f x ?? 0.2 b x m o o
? 2000 mitsubishi electric corp. new publication, effective august 2000. specifications subject to change without notice. ver 1.4 mitsubishi microcomputers 7640 group single-chip 8-bit cmos microcomputer notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customer?s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party?s rights, origina ting in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents inf ormation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that c ustomers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). ? when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for an y damage, liability or other loss resulting from the information contained herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan
rev. rev. no. date 1.4 first edition 09/05/00 revision history 7640 group data sheet (1/1) revision description

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